Abstract: A network interface circuit employing differentially driven capacitive couplings across a high voltage isolation boundary and in which a &Sgr;/&Dgr; CODEC is positioned on the line side of the high voltage interface. In this manner, only four wires cross the high voltage boundary, namely differential pairs for transmit data and receive data. The transfer functions for setting AC and DC parameters, such as impedance matching, are provided by digital filters. Further, with the CODEC on the line side of the high voltage isolation interface, the data which crosses the interface is modulated at the &Sgr;/&Dgr; data rate and, thus, capacitive coupling can be used across the high voltage isolation boundary without the loss of DC data.

Abstract: An improvement to split-architecture audio codecs such as those defined by the Audio Codec '97 specification (AC '97) includes a simulated analog-to-digital (A/D) digitization of the PC beep signal from a personal computer (PC). A PC beep simulated A/D digitization circuit simulates the A/D conversion of the PC beep signal. The PC beep simulated A/D digitization circuit eliminates the need for a pre-amplifier, and reduces the design complexity and power consumption otherwise necessary for an A/D converter, by outputting either of two simulated A/D converter values corresponding respectively to a conversion of the HIGH and LOW logic levels of the PC beep signal. The simulated A/D converter output signal from the PC beep simulated digitization circuit is subsequently scaled and summed with the digital signals from other audio sources, and output from the audio codec.

Abstract: An integrated circuit, e.g. an AC '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a DC buildup at internal nodes. The IIR filter performs a plurality of 2nd order biquadratic equations in an overall average of as few as four clock cycles per 2nd order biquad.

Abstract: An integrated circuit including a DC sensing power-up reset (PUR) circuit and method for generating a reset signal. The PUR circuit comprises a first terminal for receiving a supply voltage and a second terminal for receiving a reference voltage corresponding to a low logic state. A first transistor is coupled between the first terminal and a first node, wherein the first transistor switches on when the supply voltage is rising and exceeds a rising trip point voltage. A second transistor is coupled between the first terminal and the first node, and switches off when the supply voltage falls below a falling trip point voltage which is less than the rising trip point voltage. A first inverter is coupled at an input terminal to the first node and at an output terminal to a second node. A resistor is coupled between the first node and the second terminal.

Abstract: A network interface circuit employs an extended feedback circuit topology for impedance matching across a high voltage boundary between a line side portion and low voltage portion of a network. The network interface circuit includes an operational amplifier-based circuit which is responsive to a signal applied from user equipment on the low voltage portion. Specifically, the present invention includes a transmit path having a first, second, and third amplifier circuit and an impedance element, and a receive path that includes a transfer function implemented as a second order low pass filter for correcting amplifier gain and phase effects in the complex feedback loop of the circuit. The output impedance is remotely set by multiplying the impedance element by a scale factor to match the network impedance. The feedback loop is extended across the high voltage boundary using high voltage interfaces such as linear optical coupling devices (LOCs).

Abstract: An integrated circuit, e.g. an Audio Codec (AC) '97 conforming audio codec, includes a digital filter and gain module including multiple channels of gain control and multiple channels of digital filtering. A gain control module includes an overflow check of data samples requiring differing lengths of clamping. Each channel of the digital filter includes a finite impulse response (FIR) filter, and an infinite impulse response (IIR) filter. The digital filtering is implemented largely in hardware independent of the number of channels required and/or independent of the required order of the filtering. Thus, filter channels can be added or additional filtering implemented merely by increasing the clock speed without changing the digital filter design. The FIR filter is capable of being reset each frame to prevent a direct current (DC) buildup at internal nodes. The IIR filter performs a plurality of 2.sup.nd order biquadratic equations in an overall average of as few as four clock cycles per 2.sup.

Abstract: Briefly, in accordance with one embodiment of the invention, a bootstrap circuit comprises a pair of drivers coupled together so as to form a bootstrap node and a bipolar transistor coupled to the bootstrap node. A method of using a bipolar transistor in such a bootstrap circuit comprises the step of applying a voltage signal to the input ports of the drivers, the voltage signal having a magnitude sufficient to activate the bipolar transistor.

Abstract: A differential comparison circuit obtains an improved common mode range with respect to the voltages on first and second inputs. A first comparator is activated when the first and second input voltages are above a first level. A second comparator is activated when the first and second input voltages are below a second level. The output of the comparator that is activated is selected for providing the comparison output signal. In this manner, the comparator having improved performance, typically in terms of differential input voltage sensitivity, may be selected for the voltages present at the inputs. In a typical embodiment, the first comparator uses n-channel input devices, and the second comparator uses p-channel input devices. The activation is provided by voltage level-sensing circuitry, and may include hysteresis to help ensure reliable operation.