Patents by Inventor Jonathan James Klaren

Jonathan James Klaren has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200091876
    Abstract: Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 19, 2020
    Inventor: Jonathan James Klaren
  • Patent number: 10587225
    Abstract: A biasing circuit with high current drive capability for fast settling of a biasing voltage to a stacked cascode amplifier is presented. According to a first aspect, the biasing circuit uses transistors matched with transistors of the cascode amplifier to generate a boost current during a transition phase that changes the biasing voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the biasing circuit uses an operational amplifier in a feedback loop that forces a source node of a cascode transistor of a reference circuit, that is a scaled down replica version of the cascode amplifier, to be at a reference voltage. The high gain and high current capability of the operational amplifier, provided by isolating a high frequency signal processed by the cascode amplifier from the reference circuit, allow for a quick settling of the biasing voltage.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 10, 2020
    Assignee: pSemi Corporation
    Inventors: Jonathan James Klaren, Tero Tapio Ranta
  • Publication number: 20200036341
    Abstract: A biasing circuit with high current drive capability for fast settling of a biasing voltage to a stacked cascode amplifier is presented. According to a first aspect, the biasing circuit uses transistors matched with transistors of the cascode amplifier to generate a boost current during a transition phase that changes the biasing voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the biasing circuit uses an operational amplifier in a feedback loop that forces a source node of a cascode transistor of a reference circuit, that is a scaled down replica version of the cascode amplifier, to be at a reference voltage. The high gain and high current capability of the operational amplifier, provided by isolating a high frequency signal processed by the cascode amplifier from the reference circuit, allow for a quick settling of the biasing voltage.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Inventors: Jonathan James Klaren, Tero Tapio Ranta
  • Publication number: 20190158031
    Abstract: Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 23, 2019
    Inventors: Jonathan James Klaren, David Kovac, Eric S. Shapiro, Christopher C. Murphy, Robert Mark Englekirk, Keith Bargroff, Tero Tapio Ranta
  • Patent number: 10141907
    Abstract: Radio frequency (RF) receiver design is a challenging task, involving conflicting requirements such as tight link budget, small footprint, low insertion loss, tuning and out-of-band rejections. Methods and devices are described to allow RF receiver design meeting stringent requirements at higher frequencies while preserving a small footprint and without affecting the overall performance.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 27, 2018
    Assignee: pSemi Corporation
    Inventor: Jonathan James Klaren
  • Patent number: 10084415
    Abstract: A fast switching time is highly desired in the design of mobile handsets. The limiting factor in the switching time is the resistor through which bias is applied to amplifiers used within such handsets. Bypassing the bias resistor when amplifiers are transitioning is a way to improve switching time without compromising the RF performance. Methods and devices to generate short pulses without relying on a continuously running clock and used to bypass bias resistors are described.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: September 25, 2018
    Assignee: pSemi Corporation
    Inventor: Jonathan James Klaren