Patents by Inventor Jonathan K. Abrokwah
Jonathan K. Abrokwah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8847280Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.Type: GrantFiled: November 10, 2011Date of Patent: September 30, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
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Publication number: 20120056246Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.Type: ApplicationFiled: November 10, 2011Publication date: March 8, 2012Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
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Patent number: 8105925Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28).Type: GrantFiled: July 30, 2008Date of Patent: January 31, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
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Patent number: 7961063Abstract: A balanced-unbalanced (balun) signal transformer includes an unbalanced port, a balanced port coupled to the unbalanced port, the balanced port comprising a first terminal and a second terminal, a first capacitor coupled to the first terminal, a first inductor coupled to ground and the first capacitor, a second capacitor coupled to the second terminal, and a second inductor coupled to ground and the second capacitor. The transformer may also include a third capacitor coupled to a terminal of the unbalanced port; and a third inductor coupled to the third capacitor and the third terminal.Type: GrantFiled: July 31, 2008Date of Patent: June 14, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Lianjun Liu, Jonathan K. Abrokwah, Olin L. Hartin, Qiang Li
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Patent number: 7935607Abstract: According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) (72), is provided. An insulating dielectric layer (32) having a thickness (36) of at least 4 microns is formed over a silicon substrate (20). At least one passive electronic component (62) is formed over the insulating dielectric layer (32).Type: GrantFiled: April 9, 2007Date of Patent: May 3, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Jonathan K. Abrokwah, Keri L. Costello, James G. Cotronakis, Terry K. Daly, Jason R. Fender, Adolfo G. Reyes
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Patent number: 7842587Abstract: A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.Type: GrantFiled: January 30, 2008Date of Patent: November 30, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Matthias Passlack, Jonathan K. Abrokwah, Karthik Rajagopalan, Haiping Zhou, Richard J. Hill, Xu Li, David A. Moran, Iain G. Thayne, Peter Zurcher
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Patent number: 7683733Abstract: An electronic assembly includes a substrate (66), a balun transformer (42) formed on the substrate (66) and including a first winding (50) and a second winding (52), each having respective first and second ends, and a reaction circuit component (48) formed on the substrate (66) and electrically coupled to the second winding (52) between the first and second ends thereof. The balun transformer (42) and the reaction circuit component (48) jointly form a harmonically suppressed balun transformer having a fundamental frequency, and the reaction circuit component (48) is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency.Type: GrantFiled: February 4, 2008Date of Patent: March 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Qiang Li, Jonathan K. Abrokwah, Olin L. Hartin, Lianjun Liu
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Publication number: 20100025729Abstract: An improved insulated gate field effect device (60) is obtained by providing a substrate (20) desirably comprising a III-V semiconductor, having a further semiconductor layer (22) on the substrate (20) adapted to contain the channel (230) of the device (60) between spaced apart source-drain electrodes (421, 422) formed on the semiconductor layer (22). A dielectric layer (24) is formed on the semiconductor layer (22). A sealing layer (28) is formed on the dielectric layer (24) and exposed to an oxygen plasma (36). A gate electrode (482) is formed on the dielectric layer (24) between the source-drain electrodes (421, 422). The dielectric layer (24) preferably comprises gallium-oxide (25) and/or gadolinium-gallium oxide (26, 27), and the oxygen plasma (36) is preferably an inductively coupled plasma. A further sealing layer (44) of, for example, silicon nitride is desirably provided above the sealing layer (28).Type: ApplicationFiled: July 30, 2008Publication date: February 4, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
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Publication number: 20100026411Abstract: A balanced-unbalanced (balun) signal transformer includes an unbalanced port, a balanced port coupled to the unbalanced port, the balanced port comprising a first terminal and a second terminal, a first capacitor coupled to the first terminal, a first inductor coupled to ground and the first capacitor, a second capacitor coupled to the second terminal, and a second inductor coupled to ground and the second capacitor. The transformer may also include a third capacitor coupled to a terminal of the unbalanced port; and a third inductor coupled to the third capacitor and the third terminal.Type: ApplicationFiled: July 31, 2008Publication date: February 4, 2010Inventors: LIANJUN LIU, Jonathan K. Abrokwah, Olin L. Hartin, Qiang Li
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Publication number: 20090195324Abstract: An electronic assembly includes a substrate (66), a balun transformer (42) formed on the substrate (66) and including a first winding (50) and a second winding (52), each having respective first and second ends, and a reaction circuit component (48) formed on the substrate (66) and electrically coupled to the second winding (52) between the first and second ends thereof. The balun transformer (42) and the reaction circuit component (48) jointly form a harmonically suppressed balun transformer having a fundamental frequency, and the reaction circuit component (48) is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency.Type: ApplicationFiled: February 4, 2008Publication date: August 6, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Qiang Li, Jonathan K. Abrokwah, Olin L. Hartin, Lianjun Liu
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Publication number: 20090189252Abstract: A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.Type: ApplicationFiled: January 30, 2008Publication date: July 30, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Matthias Passlack, Jonathan K. Abrokwah, Karthik Rajagopalan, Haiping Zhou, Richard J. Hill, Xu Li, David A. Moran, Iain G. Thayne, Peter Zurcher
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Publication number: 20080246114Abstract: According to one aspect of the present invention, a method of forming a microelectronic assembly, such as an integrated passive device (IPD) (72), is provided. An insulating dielectric layer (32) having a thickness (36) of at least 4 microns is formed over a silicon substrate (20). At least one passive electronic component (62) is formed over the insulating dielectric layer (32).Type: ApplicationFiled: April 9, 2007Publication date: October 9, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Jonathan K. Abrokwah, Keri L. Costello, James G. Cotronakis, Terry K. Daly, Jason R. Fender, Adolfo C. Reyes
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Patent number: 7305223Abstract: A radio frequency (“RF”) circuit configured in accordance with an embodiment of the invention is fabricated on a substrate using integrated passive device (“IPD”) process technology. The RF circuit includes at least one RF signal line section and an integrated RF coupler located proximate to the RF signal line section. The integrated RF coupler, its output and grounding contact pads, and its matching network are fabricated on the same substrate using the same IPD process technology. The integrated RF coupler provides efficient and reproducible RF coupling without increasing the die footprint of the RF circuit.Type: GrantFiled: December 23, 2004Date of Patent: December 4, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Lianjun Liu, Jonathan K. Abrokwah, Marcus R. Ray
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Patent number: 6855965Abstract: A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).Type: GrantFiled: November 15, 2001Date of Patent: February 15, 2005Assignee: Freescale Semiconductor, Inc.Inventors: Darrell G. Hill, Mariam G. Sadaka, Jonathan K. Abrokwah
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Patent number: 6803248Abstract: A method is provided for etching quaternary interface layers of InxGa1−xAsyP1−y which are formed between layers of GaAs and InGaP in heterojunction bipolar transistors (HBTs). In accordance with the method, the interface is exposed by etching the GaAs layer with an etchant that is selective to InGaP. The interface is then etched with a dilute aqueous solution of HCl and H2O2 that is selective to InGaP. The controlled etching provided by this methodology allows HBTs to be manufactured with more sophisticated, near ideal designs which may contain multiple GaAs/InGaP interfaces.Type: GrantFiled: December 21, 2001Date of Patent: October 12, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Mariam G. Sadaka, Jonathan K. Abrokwah
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Publication number: 20030138984Abstract: A method is provided for etching quaternary interface layers of InxGa1−xAsyP1−y which are formed between layers of GaAs and InGaP in heterojunction bipolar transistors (HBTs). In accordance with the method, the interface is exposed by etching the GaAs layer with an etchant that is selective to InGaP. The interface is then etched with a dilute aqueous solution of HCl and H2O2 that is selective to InGaP. The controlled etching provided by this methodology allows HBTs to be manufactured with more sophisticated, near ideal designs which may contain multiple GaAs/InGaP interfaces.Type: ApplicationFiled: December 21, 2001Publication date: July 24, 2003Inventors: Mariam G. Sadaka, Jonathan K. Abrokwah
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Patent number: 6465297Abstract: A method of manufacturing a semiconductor component includes forming a first capacitor electrode (126) over a substrate (110), forming a capacitor dielectric layer (226) over the first capacitor electrode, and forming a second capacitor electrode (326) over the capacitor dielectric layer. The capacitor dielectric layer is made of aluminum.Type: GrantFiled: October 5, 2000Date of Patent: October 15, 2002Assignee: Motorola, Inc.Inventors: Haldane S. Henry, Darrell G. Hill, Jonathan K. Abrokwah, Mariam G. Sadaka
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Publication number: 20020053683Abstract: A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).Type: ApplicationFiled: November 15, 2001Publication date: May 9, 2002Inventors: Darrell G. Hill, Mariam G. Sadaka, Jonathan K. Abrokwah
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Patent number: 6368929Abstract: A method of manufacturing a semiconductor component and the component thereof includes forming a dielectric layer (620) over a portion of a passivation ledge (640) in an emitter layer (280) and overlapping a base contact (660) onto the dielectric layer (620).Type: GrantFiled: August 17, 2000Date of Patent: April 9, 2002Assignee: Motorola, Inc.Inventors: Darrell G. Hill, Mariam G. Sadaka, Jonathan K. Abrokwah
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Patent number: 6359294Abstract: An insulator-compound semiconductor interface structure is disclosed including compound semiconductor material with a spacer layer of semiconductor material having a bandgap which is wider than the bandgap of the compound semiconductor material positioned on a surface of the compound semiconductor material and an insulating layer positioned on the spacer layer. Minimum and maximum thicknesses of the spacer layer are determined by the penetration of the carrier wave function into the spacer layer and by the desired device performance. In a specific embodiment, the interface structure is formed in a multi-wafer epitaxial production system including a transfer and load module with a III-V growth chamber attached and an insulator chamber attached.Type: GrantFiled: March 4, 1997Date of Patent: March 19, 2002Assignee: Motorola, Inc.Inventors: Matthias Passlack, Jun Wang, Jonathan K. Abrokwah, Zhiyi Jimmy Yu