Abstract: A method of preparing crystalline alkaline earth metal oxides on a Si substrate wherein a Si substrate with amorphous silicon dioxide on a surface is provided. The substrate is heated to a temperature in a range of 700.degree. C. to 800.degree. C. and exposed to a beam of alkaline earth metal(s) in a molecular beam epitaxy chamber at a pressure within approximately a 10.sup.-9 -10.sup.-10 Torr range. During the molecular beam epitaxy the surface is monitored by RHEED technique to determine a conversion of the amorphous silicon dioxide to a crystalline alkaline earth metal oxide. Once the alkaline earth metal oxide is formed, additional layers of material, e.g. additional thickness of an alkaline earth metal oxide, single crystal ferroelectrics or high dielectric constant oxides on silicon for non-volatile and high density memory device applications.

Abstract: A method of passivating the surface of a Si wafer is disclosed including the steps of cleaning the surface of the Si wafer and depositing an alkaline earth metal on the clean surface at a wafer temperature in a range of approximately 400.degree. C. to 750.degree. C. The surface is monitored during deposition to detect a (4.times.2) surface reconstruction pattern indicating approximately a one-quarter monolayer of alkaline earth metal is formed. The wafer is annealed at a temperature in a range of 800.degree. C. to 900.degree. C. until the alkaline earth metal forms an alkaline earth metal silicide with a (2.times.1) surface pattern on the surface.

Abstract: A production process for protecting the surface of compound semiconductor wafers includes providing a multi-wafer epitaxial production system with a transfer and load module, a III-V growth chamber and an insulator chamber. The wafer is placed in the transfer and load module and the pressure is reduced to .ltoreq.10.sup.-10 Torr, after which the wafer is moved to the III-V growth chamber and layers of compound semiconductor material are epitaxially grown on the surface of the wafer.

Abstract: A method of passivating interface states of oxide-compound semiconductor interfaces using molecular, atomic, or isotopic species wherein said species are applied before oxide deposition in ultra-high vacuum, or during interruption of oxide deposition in ultra-high vacuum (preferentially after oxide surface coverage of a submonolayer, a monolayer, or a few monolayers), or during oxide deposition in ultra-high vacuum, or after completion of oxide deposition, or before or after any processing steps of the as deposited interface structure. In a preferred embodiment, hydrogen or deuterium atoms are applied to a Ga.sub.2 O.sub.3 --GaAs interface at some point before, during, or after oxide deposition in ultra-high vacuum, or before or after any processing steps of the as deposited interface structure, at any given and useful substrate temperature wherein the atomic species can be provided by any one of RF discharge, microwave plasma discharge, or thermal dissociation.

Abstract: A method of forming a thin silicide layer on a silicon substrate 12 including heating the surface of the substrate to a temperature of approximately 500.degree. C. to 750.degree. C. and directing an atomic beam of silicon 18 and an atomic beam of an alkaline-earth metal 20 at the heated surface of the substrate in a molecular beam epitaxy chamber at a pressure in a range below 10.sup.-9 Torr. The silicon to alkaline-earth metal flux ratio is kept constant (e.g. Si/Ba flux ratio is kept at approximately 2:1) so as to form a thin alkaline-earth metal silicide layer (e.g. BaSi.sub.2) on the surface of the substrate. The thickness is determined by monitoring in situ the surface of the single crystal silicide layer with RHEED and terminating the atomic beam when the silicide layer is a selected submonolayer to one monolayer thick.

Abstract: A method of fabricating submicron HFETs includes forming a buffered substrate structure with a supporting substrate of GaAs, a portion of low temperature AlGaAs grown on the supporting substrate at a temperature of approximately 300.degree. C., a layer of low temperature GaAs grown on the portion AlGaAs layer at a temperature of 200.degree. C., a layer of low temperature AlGaAs grown on the GaAs layer at a temperature of 400.degree. C., and a buffer layer of undoped GaAs grown on the second AlGaAs layer. Complementary pairs of HFETs can be formed on the buffered substrate structure, since the structure supports the operation of p and n type transistors equally well.

Abstract: A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.

Abstract: A method of fabricating a gate quality oxide-compound semiconductor structure includes forming an insulating Ga.sub.2 O.sub.3 layer on the surface of a compound semiconductor wafer structure by a supersonic gas jet containing gallium oxide molecules and oxygen. In a preferred embodiment, a III-V compound semiconductor wafer structure with an atomically ordered and chemically clean semiconductor surface is transferred from a semiconductor growth chamber into an insulator deposition chamber via an ultra high vacuum preparation chamber. Ga.sub.2 O.sub.3 deposition onto the surface of the wafer structure is initiated by a supersonic gas jet pulse and proceeds via optimization of pulse duration, speed of gas jet, mole fraction of gallium oxide molecules and oxygen atoms, and plasma energy.

Abstract: A method of thermal processing a supporting structure comprised of various compound semiconductor layers having a Gd free Ga.sub.2 O.sub.3 surface layer including coating the surface layer with a dielectric or a metallic cap layer or combinations thereof, such that the low D.sub.it Ga.sub.2 O.sub.3 -compound semiconductor structure is conserved during thermal processing, e.g. during activation of ion implants of a self aligned metal-oxide-compound semiconductor gate structure. In a preferred embodiment, the semiconductor structure has a surface of GaAs, the Gd free Ga.sub.2 O.sub.3 layer has a thickness in a range of approximately 1 nm to 20 nm, and the insulating or metallic cap layer has a thickness in a range of approximately 1 nm to 500 nm.

Abstract: A heterostructure field effect transistor and method including at least one passivation layer (20) and at least one etch stop layer (22). Enhancement, depletion and combined devices with both enhancement mode and depletion mode devices are possible with minor process variations. Refractory gate (40) and non-gold refractory ohmic contact (52) metallization combined with other features allows non-liftoff metal patterning.

Abstract: An N-type HIGFET (10) utilizes two etch layers (17,18) to form a gate insulator (16) to be shorter that the gate electrode (21). This T-shaped gate structure facilitates forming source (23) and drain (24) regions that are separated from the gate insulator (16) by a distance (22) in order to reduce leakage current and increase the breakdown voltage.

Abstract: A HIGFET (10) utilizes an etch stop layer (17) to form a gate insulator (16) to be narrower than the gate electrode (21). This T-shaped gate structure facilitates forming source (23) and drain (24) regions that are separated from the gate insulator (16) by a distance (22) in order to reduce leakage current and increase the breakdown voltage.

Abstract: A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the InGaAs channel layer (16) to provide improved ohmic contact, despite the fact that the structure incorporates an advantageous high aluminum composition barrier layer (18) and an advantageous GaAs cap layer (20).

Abstract: A method of forming a dielectric layer on a supporting structure of III-V material having a clean and atomically ordered surface to be coated with a dielectric layer including the step of depositing a layer of Ga.sub.2 O.sub.3, having a sublimation temperature, on the surface of the supporting structure by evaporation using a high purity single crystal of material including Ga.sub.2 O.sub.3 and a second oxide with a melting point greater than 700.degree. C. above the sublimation temperature of the Ga.sub.2 O.sub.3. The evaporation can be performed by any one of thermal evaporation, electron beam evaporation, and laser ablation.

Abstract: A semiconductor device with an improved insulating and passivating layer including the steps of providing a gallium arsenide substrate with a surface, and crystallographically lattice matching an insulating and passivating layer of indium gallium fluoride on the surface of the gallium arsenide substrate. In one embodiment the semiconductor device is a FET and the layer of indium gallium fluoride covers at least an inter-channel area surrounding the gate.

Abstract: An N-type HIGFET (10) utilizes two etch layers (17,18) to form a gate insulator (16) to be shorter that the gate electrode (21). This T-shaped gate structure facilitates forming source (23) and drain (24) regions that are separated from the gate insulator (16) by a distance (22) in order to reduce leakage current and increase the breakdown voltage.

Abstract: A manufacturable III-V semiconductor structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

Abstract: The present invention encompasses a complementary semiconductor device having the same type of material providing the ohmic contacts (117, 119) to both the N-type and P-type devices. In a preferred embodiment, P-source and P -drain regions ( 80, 82 ) are heavily doped with a P-type impurity (81, 83) so that an ohmic with N-type impurity can be used as an ohmic contact. One ohmic material that may be used is nickel-germanium-tungsten. Nickel-germanium-tungsten is etchable, and therefore does not require lift-off processing. Furthermore, a preferred complementary semiconductor device made in accordance with the present invention is compatible with modern aluminum based VLSI interconnection processes.

Abstract: A layer is plasma etched or deposited with a gaseous mixture of a hydrocarbon, hydrogen and a noble gas. A cathode DC bias of greater than 600 V is used. This cathode DC bias allows for selectively etching a III-V material over an aluminum containing layer or for the deposition of a hydrogenated carbon film.

Abstract: The present invention encompasses a method for providing the same ohmic material contact (120, 122, 124) to N-type and P-type regions (70, 80) of a III-V semiconductor device. Specifically, an N-type region (70) extending through a semiconductor structure is formed. Additionally, a P-type region (80) extending through the substrate is formed. The P-type region (80) may be heavily doped with P-type impurities (81). A first ohmic region (117) is formed, contacting the N-type region (70). The first ohmic region may comprise an ohmic material including metal and an N-type dopant. A second ohmic region (119) is formed, contacting the P-type region (80, 81). The second ohmic region comprises the same ohmic material as the first ohmic region. One ohmic material that may be used is nickel-germanium-tungsten.