Abstract: An improvement to a phase and frequency detector (PFD) employs an additional reset control that acts to effectively reset the registers that generate the phase indicator signals if an undesirable preconditioned state has been entered. The additional reset control signal is generated by a register that is enabled upon detection of the preconditioned state. The new reset control signal is activated upon detection of a synchronizing signal, that is based on an input source signal, while the enable control is active. The improved detector can allows a phase locked loop (PLL) system locking to the nearest input reference clock edge and it can provide immunity to missing input clock edges.

Abstract: A clock output controller using a digital frequency synthesis minimizes the clock output disturbance due to input reference signal switchover. The controller includes a first and a second accumulator where the Most Significant Bit (MSB) of the first accumulator output generates the clock output signal and the MSB of the second accumulator generates a feedback signal. A reset control signal is generated by the transition edge detector/switchover controller and it is coupled to the register block of the second accumulator in order to reset the feedback signal at an appropriate time so as to match the phase of the new reference signal. A hold control signal is also generated to keep the clock output locked on the old reference signal until the feedback signal is locked to the new signal. The hold signal is then reset once locking to the new reference signal is accomplished and the clock output is fully switched over with minimal disturbance.

Abstract: A slave clock generation system and method suitable for use with synchronous telecommunications networks generates one or more slave clocks from a selected reference clock using a direct digital synthesis technique. A multiplexer selects a reference clock from a number of available sources, each of which can be at its own spot frequency, based on a predetermined selection order. Toggle detectors monitor each of the available clock sources, and block the selection of any that are not within a specified frequency range. A local oscillator establishes short-term and long-term measurement periods; the cycles of the selected reference clock are counted over consecutive short-term measurement periods to determine the relative frequency of the selected clock with respect to the frequency of the local oscillator. The cycle counts are fed to a phase-to-clock converter, which produces a slave clock output having a frequency that varies with the relative frequency measured for the selected clock.