Patents by Inventor JONATHAN M. EASTEP
JONATHAN M. EASTEP has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11740673Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.Type: GrantFiled: January 5, 2021Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Jonathan M. Eastep, Richard J. Greco
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Patent number: 11650652Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: GrantFiled: June 24, 2021Date of Patent: May 16, 2023Assignee: INTEL CORPORATIONInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
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Patent number: 11372464Abstract: An apparatus is provided which comprises: a controller to allocate, to a component, a resource budget selected from a plurality of quantization levels; and a circuitry to adaptively update the plurality of quantization levels.Type: GrantFiled: September 28, 2017Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Fuat Keceli, Frederico Ardanaz, Jonathan M. Eastep, Ankush Varma, Krishnakanth V. Sistla
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Patent number: 11194373Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.Type: GrantFiled: April 20, 2020Date of Patent: December 7, 2021Assignee: Intel CorporationInventors: Asma Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Nikhil Gupta, Ankush Varma, Krishnakanth V. Sistla, Ian M. Steiner
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Publication number: 20210325952Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: ApplicationFiled: June 24, 2021Publication date: October 21, 2021Applicant: INTEL CORPORATIONInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
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Patent number: 11144085Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.Type: GrantFiled: June 23, 2017Date of Patent: October 12, 2021Assignee: Intel CorporationInventors: Asma H. Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Dorit Shapira, Krishnakanth Sistla, Nikhil Gupta, Vasudevan Srinivasan, Chris MacNamara
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Publication number: 20210247829Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: January 5, 2021Publication date: August 12, 2021Applicant: Intel CorporationInventors: Jonathan M. Eastep, Richard J. Greco
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Patent number: 11061460Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for Thermal Design Power (TDP) rebalancing among thermally-coupled processors and non-thermally-coupled processors, providing computing efficiency or homogeneity with respect to, including but not limited to, thermal requirements, power consumption, and processor operations. The TDP rebalancing may include implementing management circuitry and configuration control circuitry. Other embodiments may be described and claimed.Type: GrantFiled: June 28, 2019Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Fuat Keceli, Tozer J. Bandorawalla, Grant McFarland, Jonathan M. Eastep, Federico Ardanaz
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Patent number: 11061463Abstract: Apparatus, systems, and methods provide an interface between a plurality of hardware resources of a node and a power manager. The interface is configured to define one or more resource groups to expose to the power manager for power measurement and control, assign the plurality of hardware resources to the one or more resource groups, and provide a power allowance to each resource group.Type: GrantFiled: August 29, 2017Date of Patent: July 13, 2021Assignee: Intel CorporationInventors: Federico Ardanaz, Jonathan M. Eastep, Richard J. Greco, Ramkumar Nagappan, Alan B. Kyker
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Patent number: 11048313Abstract: Described herein are automated hierarchical feed-back driven control mechanisms and methods, including an apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to receive a system operating characteristic guidance. The second circuitry may be operable to provide one or more manufacturing characteristics. The third circuitry may be operable to store one or more system operating characteristics based upon the system operating characteristic guidance and the one or more manufacturing characteristics.Type: GrantFiled: March 29, 2019Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Siddhartha Jana, Federico Ardanaz, Jonathan M. Eastep, Yaxin Shui, Keith Underwood
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Patent number: 10884471Abstract: Methods and apparatus to provide holistic global performance and power management are described. In an embodiment, logic (e.g., coupled to each compute node of a plurality of compute nodes) causes determination of a policy for power and performance management across the plurality of compute nodes. The policy is coordinated across the plurality of compute nodes to manage a job to one or more objective functions, where the job includes a plurality of tasks that are to run concurrently on the plurality of compute nodes. Other embodiments are also disclosed and claimed.Type: GrantFiled: October 16, 2018Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Jonathan M. Eastep, Richard J. Greco
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Publication number: 20200319693Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.Type: ApplicationFiled: April 20, 2020Publication date: October 8, 2020Applicant: Intel CorporationInventors: Asma Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Nikhil Gupta, Ankush Varma, Krishnakanth V. Sistla, Ian M. Steiner
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Publication number: 20200310515Abstract: Described herein are automated hierarchical feed-back driven control mechanisms and methods, including an apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to receive a system operating characteristic guidance. The second circuitry may be operable to provide one or more manufacturing characteristics. The third circuitry may be operable to store one or more system operating characteristics based upon the system operating characteristic guidance and the one or more manufacturing characteristics.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Applicant: Intel CorporationInventors: Siddhartha Jana, Federico Ardanaz, Jonathan M. Eastep, Yaxin Shui, Keith Underwood
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Patent number: 10719320Abstract: An apparatus is provided which comprises: a component; a voltage generator to supply load current to the component; first one or more circuitries to predict that the load current is to increase from a first time; and second one or more circuitries to, in anticipation of the increase in the load current from the first time, cause the component to execute first instructions during a time period that occurs prior to the first time.Type: GrantFiled: July 31, 2017Date of Patent: July 21, 2020Assignee: Intel CorporationInventors: Federico Ardanaz, Roger Gramunt, Jesus Corbal, Dennis R. Bradford, Jonathan M. Eastep
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Patent number: 10627885Abstract: Various embodiments comprise prioritizing frequency allocations in thermally- or power-constrained computing devices. Computer elements may be assigned ‘weights’ based on their priorities. The computer elements with higher weights may receive higher frequency allocations to assure they receive priority in processing more quickly. The computer elements with lower weights may receive lower frequency allocations and suffer a slowdown in their processing. Elements with the same weight may be grouped together for the purpose of frequency allocation.Type: GrantFiled: January 9, 2018Date of Patent: April 21, 2020Assignee: Intel CorporationInventors: Asma Al-Rawi, Federico Ardanaz, Jonathan M. Eastep, Nikhil Gupta, Ankush Varma, Krishnakanth V. Sistla, Ian M. Steiner
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Patent number: 10620687Abstract: Methods and apparatus to provide a hybrid power management approach are described. Some embodiments redefine the interface to Power Control Unit (PCU) allowing a hybrid implementation where software running on CPU (Central Processing Unit, also referred to herein interchangeably as “processor”) cores performs more of the work for power management, enabling the PCU to remain as a simple or regular microcontroller. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 22, 2014Date of Patent: April 14, 2020Assignee: Intel CorporationInventors: Jonathan M. Eastep, Richard J. Greco, Federico Ardanaz
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Patent number: 10521002Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.Type: GrantFiled: October 19, 2017Date of Patent: December 31, 2019Assignee: INTEL CORPORATIONInventors: Jonathan M. Eastep, Rohit Banerjee, Richard J. Greco, Ilya Sharapov, David N. Lombard, Hari K. Nagpal
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Patent number: 10469347Abstract: Systems, apparatuses and methods may provide for a plurality of node-level agents, wherein each node-level agent aggregates network statistics information from a plurality of probes associated with a communications interface. Additionally, one or more job-level agents may be communicatively coupled to the plurality of node-level agents, wherein each job-level agent aggregates network statistics information from two or more of the node-level agents. Moreover, a system-level agent may be communicatively coupled to the job-level agent(s). The system-level agent may generate a power model based on aggregated network statistics information from the job-level agent(s) and propagate the power model to the node-level agents via the job-level agent(s).Type: GrantFiled: March 25, 2016Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Jonathan M. Eastep, Eric R. Borch
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Patent number: 10466754Abstract: Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.Type: GrantFiled: December 26, 2014Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Jonathan M. Eastep, Ilya Sharapov, Richard J. Greco, Steve S. Sylvester, David N. Lombard
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Publication number: 20190324517Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for Thermal Design Power (TDP) rebalancing among thermally-coupled processors and non-thermally-coupled processors, providing computing efficiency or homogeneity with respect to, including but not limited to, thermal requirements, power consumption, and processor operations. The TDP rebalancing may include implementing management circuitry and configuration control circuitry. Other embodiments may be described and claimed.Type: ApplicationFiled: June 28, 2019Publication date: October 24, 2019Inventors: Fuat Keceli, Tozer J. Bandorawalla, Grant McFarland, Jonathan M. Eastep, Federico Ardanaz