Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.

Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: An integrated circuit system has a die with first and second sides, and contains high frequency circuitry operating at mm-wave frequencies. The system also has a plurality of interfaces (on the first side) in electrical communication with the high frequency circuitry, and a heat sink having a bottom surface with a first region and an aperture region. The first region is in physical and conductive contact with the die, while the aperture region forms a concavity with an inner concave surface that is spaced from the die.

Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar substrate. Each integrated circuit is a high frequency integrated circuit configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array. In addition, each integrated circuit has a substrate side coupled with the laminar substrate, and a back side. The phased array also has a plurality of heat sinks. Each integrated circuit is coupled with at least one of the heat sinks. At least one of the integrated circuits has a thermal interface material in conductive thermal contact with its back side. The thermal interface material thus is between the at least one integrated circuit and one of the heat sinks. Preferably, the thermal interface material has a magnetic loss tangent value of between 0.5 and 4.5.

Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be preprogrammed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.

Abstract: A frequency conversion circuit having a plurality of N signal channels, each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each channel includes: a sampler coupled the input signal and being responsive to sampling signals; and a controllable time delay for producing the train of sampling signals in response to the train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N.

Abstract: An interfering signal canceller for cancelling an interfering signal component of an input signal includes a voltage sensor element disposed in a primary path and fed by the input signal, a coupler disposed in the primary path and fed by the voltage sensor element, a Hartley image-reject element disposed in an auxiliary path and fed by the input signal for converting the input signal to an intermediate or baseband frequency signal, a phase slope compensator disposed in the auxiliary path after the Hartley image-reject element to allow broadband phase adjustment of the interfering signal component of a converted input signal, and an inverse Hartley image-reject element disposed in the auxiliary path after the phase phase slope compensator to convert the passed the interfering signal component to the predetermined band of frequencies and having an output fed to the coupler.

Abstract: A semiconductor structure provided having: a dielectric; a non-column III-V doped semiconductor layer disposed over the dielectric; and an isolation barrier comprising column III-V material disposed vertically through the semiconductor layer to the dielectric. In one embodiment, the semiconductor layer is silicon and has CMOS transistors disposed in the semiconductor layer above a first region of the dielectric and a III-V transistor disposed above a different region of the dielectric. The barrier electrically isolates the column III-V transistor from the CMOS transistors. In one embodiment, the structure includes a passive device disposed over the semiconductor layer and a plurality of laterally spaced III-V structures, the III-V structures being disposed under the passive device, the III-V structures passing vertically through the semiconductor layer to the insulating layer.

Abstract: An antenna array includes a plurality of antenna elements. The antenna elements include layers of dielectric material; an antenna inlaid in a top layer of the dielectric material so a surface of the antenna is substantially parallel to an outer surface of the top layer of dielectric material; and a conductive balun, coupled to the antenna, and embedded in one or more layers of the dielectric material. The antenna array is operative to receive signals from V to W frequency band transmissions generated by a heat source.

Abstract: Embodiments of a wideband interference mitigation (IM) system with negative group delay (NGD) compensation and method for wideband interference cancellation are generally described herein. In some embodiments, the wideband IM system may include first frequency-selective circuitry to capture interfering signals within a bandwidth of interest from a primary signal path after removal of a desired signal, cancellation circuitry to implement a negative group delay (NGD) on output signals from the first frequency-selective circuitry to generate negative group-delayed signals, and second frequency-selective circuitry to generate interference cancellation signals from the negative group-delayed signals for combining with signals from the primary signal path.

Abstract: A frequency conversion circuit having a plurality of N signal channels, each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each signal channel includes: a column III-V semiconductor sampler coupled the input signal and being responsive to sampling signals; and a column IV semiconductor controllable time delay for producing the train of sampling signals in response to a train of pulses produced on the column IV semiconductor, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N.

Abstract: A frequency conversion circuit having a plurality of N signal channels, each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each channel includes: a sampler coupled the input signal and being responsive to sampling signals; and a controllable time delay for producing the train of sampling signals in response to the train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the to trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N.

Abstract: A frequency conversion circuit having a plurality of N signal channels, each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each signal channel includes: a column III-V semiconductor sampler coupled the input signal and being responsive to sampling signals; and a column IV semiconductor controllable time delay for producing the train of sampling signals in response to a train of pulses produced on the column IV semiconductor, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N.

Abstract: Embodiments of a wideband interference mitigation (IM) system with negative group delay (NGD) compensation and method for wideband interference cancellation are generally described herein. In some embodiments, the wideband IM system may include first frequency-selective circuitry to capture interfering signals within a bandwidth of interest from a primary signal path after removal of a desired signal, cancellation circuitry to implement a negative group delay (NGD) on output signals from the first frequency-selective circuitry to generate negative group-delayed signals, and second frequency-selective circuitry to generate interference cancellation signals from the negative group-delayed signals for combining with signals from the primary signal path.

Abstract: An antenna array includes a plurality of antenna elements. The antenna elements include layers of dielectric material; an antenna inlaid in a top layer of the dielectric material so a surface of the antenna is substantially parallel to an outer surface of the top layer of dielectric material; and a conductive balun, coupled to the antenna, and embedded in one or more layers of the dielectric material. The antenna array is operative to receive signals from V to W frequency band transmissions generated by a heat source.

Abstract: A semiconductor structure provided having: a dielectric; a non-column III-V doped semiconductor layer disposed over the dielectric; and an isolation barrier comprising column III-V material disposed vertically through the semiconductor layer to the dielectric. In one embodiment, the semiconductor layer is silicon and has CMOS transistors disposed in the semiconductor layer above a first region of the dielectric and a III-V transistor disposed above a different region of the dielectric. The barrier electrically isolates the column III-V transistor from the CMOS transistors. In one embodiment, the structure includes a passive device disposed over the semiconductor layer and a plurality of laterally spaced III-V structures, the III-V structures being disposed under the passive device, the III-V structures passing vertically through the semiconductor layer to the insulating layer.

Abstract: A phase shifter-attenuator system having: a controller for producing a digital word representative of a predetermined phase shift and attenuation provided to an input signal; and a phase shifter-attenuation section. The phase shifter-attenuation section includes: a phase rotator for providing one of a plurality combinations of phase shifts-attenuation states to the input signal selectively in accordance with one portion of the produced digital word; and an attenuation section for distributing the plurality of combinations of phase shift-attenuation states over a selected range of attenuations, such range being selected in accordance with a second portion of the produced digital word.

Abstract: An interfering signal canceller has a passive isolation element fed by an input signal in a primary path. A first frequency converter is in an auxiliary path and is fed by an input signal for converting the input signal to an intermediate or baseband signal. A bandpass filter is tuned to the interfering signal component for passing the interfering signal component of the converted input signal and suppressing the desired signal component. A second frequency converter/phase rotator section has a phase rotator fed by a local oscillator signal and a second frequency converter fed by the phase rotator and the bandpass filter. The second frequency converter/phase rotator section convert and phase adjust the passed the interfering signal component and the suppressed desired signal component to the predetermined band of frequencies. A combiner combines signals in the primary signal path and from the second frequency converter/phase rotator section.

Abstract: A harmonic rejection mixer having a phase rotator fed by a local oscillator signal. The local oscillator signal has a reference frequency. The phase rotator produces a plurality of output signals, each one of the signals having a common frequency related to the reference frequency and having different relative phase shifts. A plurality of mixer sections, each one of the sections being fed an input signal and a corresponding one of the plurality of output signals mixes the local oscillator signal with the corresponding one of the plurality of output signals fed thereto. A combiner combines the mixer signal from the plurality of mixer sections into a composite output signal. A detector detects energy in a harmonic of the composite signal and for adjusting the output signal of the phase rotator to reduce the selected harmonic of the composite signal.