Abstract: Described is an apparatus for providing spread-spectrum to a clock signal. The apparatus comprises: an oscillator to generate an output clock signal, the oscillator to receive an adjustable reference signal to adjust frequency of the output clock signal; a first circuit to provide a first signal indicative of a center frequency of the output clock signal; a second circuit to generate a switching waveform to provide spread-spectrum for the output clock signal; and a third circuit, coupled to the first and second circuits, to provide the adjustable reference signal according to the first signal and the switching waveform.

Abstract: Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to perform chopping to cancel common-mode noise; and one or more counters coupled to the sigma-delta modulator to generate a digital code representative of the analog signal.

Abstract: In one embodiment, the present invention includes a method for determining if a system is compatible with an upgrade to a hardware resource of the system, receiving instructions from a remote server to upgrade the hardware resource if the system is compatible, and programming the hardware resource based on the instructions. In one such embodiment, the hardware resource may be programmed via programmable fuses to enable circuitry of the hardware resource. Other embodiments are described and claimed.

Abstract: Techniques for preventing an integrated circuit (IC) from overheating are described herein. According to one embodiment, an exemplary process includes detecting whether a temperature of an integrated circuit (IC) exceeds a threshold independent of an operating state of the IC, and removing at least a portion of a power from the IC if the temperature of the IC exceeds the threshold. Other methods and apparatuses are also described.

Abstract: In one embodiment, the present invention includes a method for determining if a system is compatible with an upgrade to a hardware resource of the system, receiving instructions from a remote server to upgrade the hardware resource if the system is compatible, and programming the hardware resource based on the instructions. In one such embodiment, the hardware resource may be programmed via programmable fuses to enable circuitry of the hardware resource. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for determining if a system is compatible with an upgrade to a hardware resource of the system, receiving instructions from a remote server to upgrade the hardware resource if the system is compatible, and programming the hardware resource based on the instructions. In one such embodiment, the hardware resource may be programmed via programmable fuses to enable circuitry of the hardware resource. Other embodiments are described and claimed.

Abstract: A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.

Abstract: An apparatus and a system, as well as a method and article, may operate to compare a circuit operational condition with a specified condition, to record an out-of-specification condition, and to determine some specified number of recorded out-of-specification conditions.

Abstract: An apparatus, a method, and a system for a fuse cell array are disclosed herein. A plurality of fuse cells are arranged in an array. One or more fuse cells include a pair of fuse devices to output a pair of voltages, respectively, wherein the pair of fuse devices are redundantly programmed. A sense amplifier is coupled to the plurality of fuse cells to read the pair of voltage outputs from each of the plurality of fuse cells, respectively. A comparator circuit is coupled to the sense amplifier to compare the pair of voltage outputs for each of the plurality of fuse cells and to output the compared result.

Abstract: Techniques for preventing an integrated circuit (IC) from overheating are described herein. According to one embodiment, an exemplary process includes detecting whether a temperature of an integrated circuit (IC) exceeds a threshold independent of an operating state of the IC, and removing at least a portion of a power from the IC if the temperature of the IC exceeds the threshold. Other methods and apparatuses are also described.

Abstract: Techniques for preventing an integrated circuit (IC) from overheating are described herein. According to one embodiment, an exemplary process includes detecting whether a temperature of an integrated circuit (IC) exceeds a threshold independent of an operating state of the IC, and removing at least a portion of a power from the IC if the temperature of the IC exceeds the threshold. Other methods and apparatuses are also described.

Abstract: A pipelined instruction decoder for a multithread processor including an instruction decode pipeline, a valid bit pipeline, and a thread identification pipeline in parallel together, with each having the same predetermined number of pipe stages. The instruction decode pipeline to decode instructions associated with a plurality of instruction threads. The valid bit pipeline to associate a valid indicator at each pipe stage with each instruction being decoded in the instruction decode pipeline. The thread identification pipeline to associate a thread-identification at each pipestage with each instruction being decoded in the instruction decode pipeline. The pipelined instruction decoder may further include a pipeline controller to control the clocking of each pipe stage of the instruction decode pipeline, the valid bit pipeline, and the thread identification pipeline.

Abstract: In a system where multiple instruction pipes share access to a common return stack buffer (RSB), coordination is provided to ensure that no instruction pipe gains unfair access to the RSB. Additionally, further coordination control may be provided to ensure that a pipe operates upon valid data notwithstanding communication delays that may be present in a communication path between the pipe and the RSB. In one embodiment, if a system must gain access to the RSB, it determines with reference to prior accesses to the RSB whether immediate access the RSB would exceed a predetermined access rate. If so, it delays its attempt to access the RSB until it re-synchronizes to the access rate. In another embodiment, it delays use of data from the RSB until communication delays are overcome.

Abstract: Techniques for preventing an integrated circuit (IC) from overheating are described herein. According to one embodiment, an exemplary process includes detecting whether a temperature of an integrated circuit (IC) exceeds a threshold independent of an operating state of the IC, and removing at least a portion of a power from the IC if the temperature of the IC exceeds the threshold. Other methods and apparatuses are also described.

Abstract: According to some embodiments, a reference voltage signal initially increases with increases in a processor voltage signal and then decreases with a further increase in the processor voltage signal. Moreover, according to some embodiments a comparator circuit generates a power indication signal when a substantially scaled processor voltage signal exceeds a reference voltage signal.

Abstract: According to some embodiments, a reference voltage signal initially increases with increases in a processor voltage signal and then decreases with a further increase in the processor voltage signal. Moreover, according to some embodiments a comparator circuit generates a power indication signal when a substantially scaled processor voltage signal exceeds a reference voltage signal.

Abstract: A multithread pipelined instruction decoder to clock, clear and stall an instruction decode pipeline of a multi-threaded machine to maximize performance and minimize power. A shadow pipeline shadows the instruction decode pipeline maintaining a the thread-identification and instruction-valid bits for each pipestage of the instruction decoder. The thread-id and valid bits are used to control the clear, clock, and stall of each pipestage of the instruction decoder. Instructions of one thread can be cleared without impacting instructions of another thread in the decode pipeline. In some cases, instructions of one thread can be stalled without impacting instructions of another thread in the decode pipeline. In the present invention, pipestages are clocked only when a valid instruction needs to advance in order to conserve power and to minimize stalling.

Abstract: According to some embodiments, a reference voltage signal initially increases with increases in a processor voltage signal and then decreases with a further increase in the processor voltage signal. Moreover, according to some embodiments a comparator circuit generates a power indication signal when a substantially scaled processor voltage signal exceeds a reference voltage signal.

Abstract: According to some embodiments, a reference voltage signal initially increases with increases in a processor voltage signal and then decreases with a further increase in the processor voltage signal. Moreover, according to some embodiments a comparator circuit generates a power indication signal when a substantially scaled processor voltage signal exceeds a reference voltage signal.

Abstract: A method of linear space target address generation for a relative branch is described. The method includes generating a selection signal, and generating a linear space target address using the selection signal by generating a plurality of corrected target addresses and selecting the linear space target address from the plurality of corrected target addresses using the selection signal.