Patents by Inventor Jonathan P. Douglas

Jonathan P. Douglas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6609193
    Abstract: A multithread pipelined instruction decoder to clock, clear and stall an instruction decode pipeline of a multi-threaded machine to maximize performance and minimize power. A shadow pipeline shadows the instruction decode pipeline maintaining a the thread-identification and instruction-valid bits for each pipestage of the instruction decoder. The thread-id and valid bits are used to control the clear, clock, and stall of each pipestage of the instruction decoder. Instructions of one thread can be cleared without impacting instructions of another thread in the decode pipeline. In some cases, instructions of one thread can be stalled without impacting instructions of another thread in the decode pipeline. In the present invention, pipestages are clocked only when a valid instruction needs to advance in order to conserve power and to minimize stalling.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: August 19, 2003
    Assignee: Intel Corporation
    Inventors: Jonathan P. Douglas, Daniel J. Deleganes, James D. Hadley
  • Publication number: 20030079105
    Abstract: A method of linear space target address generation for a relative branch is described. The method includes generating a selection signal, and generating a linear space target address using the selection signal by generating a plurality of corrected target addresses and selecting the linear space target address from the plurality of corrected target addresses using the selection signal.
    Type: Application
    Filed: November 12, 2002
    Publication date: April 24, 2003
    Inventors: Jonathan P. Douglas, Alan B. Kyker
  • Patent number: 6502177
    Abstract: A method and circuit for linear space target address generation for a relative branch is described. A selection signal is generated to be used in generating a linear space target address. The generation of the linear space target address includes generating multiple corrected target addresses and selecting the linear space target address from the multiple corrected target addresses using the selection signal. The process of generating multiple corrected target addresses includes generating first, second, and third corrected target addresses. The first corrected target address is generated using an address and a displacement. The second corrected target address is generated using the address, displacement, and a second adder correction value. The third corrected target address is generated using the address, displacement, and a third adder correction value. A multiplexer outputs the first, second, or third corrected target address using the selection signal.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: December 31, 2002
    Assignee: Intel Corporation
    Inventors: Jonathan P. Douglas, Alan B. Kyker