Patents by Inventor Jonathan Reid

Jonathan Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8475636
    Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: July 2, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Steven Mayer, Jingbin Feng, Zhian He, Jonathan Reid, Seshasayee Varadarajan
  • Patent number: 8475644
    Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: July 2, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Steven Mayer, Jingbin Feng, Zhian He, Jonathan Reid, Seshasayee Varadarajan
  • Publication number: 20130156555
    Abstract: Braze materials, brazing processes, and coatings produced therefrom, for example, a wear-resistant coating suitable for protecting surfaces subjected to wear at high temperatures. The braze material includes first particles formed of a metallic alloy and second particles formed of a cobalt-base braze alloy having a melting point below the melting point of the first particles. The braze alloy consists of, by weight, 3.5 to 15.0% silicon, 2.0 to 6.0% boron, and the balance cobalt and incidental impurities, and the second particles constitute at least 30 up to 90 weight percent of the first and second particles combined. Following a brazing cycle performed on the braze material, a wear-resistant coating is formed in which the first particles are dispersed in a matrix of the braze alloy.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: David Edwin Budinger, Jonathan Reid Biberstine
  • Patent number: 8377824
    Abstract: Apparatus and methods for depositing copper on tungsten are presented. The invention finds particular use in the semiconductor industry for depositing copper seed layers onto fields or through silicon vias having tungsten barrier layers, both reducing cost and complexity of existing methods.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: February 19, 2013
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan Reid, Sesha Varadarajan, Ugur Emekli
  • Patent number: 8308931
    Abstract: An apparatus for electroplating a layer of metal on the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer (preferably within 5 mm of the wafer surface) which serves to modulate ionic current at the wafer surface, and a second cathode configured to divert a portion of current from the wafer surface. The ionically resistive ionically permeable element in a preferred embodiment is a disk made of a resistive material having a plurality of perforations formed therein, such that perforations do not form communicating channels within the body of the disk. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: November 13, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan Reid, Bryan Buckalew, Zhian He, Seyang Park, Seshasayee Varadarajan, Bryan Pennington, Thomas Ponnuswamy, Patrick Breling, Glenn Ibarreta, Steven Mayer
  • Publication number: 20120279864
    Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.
    Type: Application
    Filed: October 31, 2011
    Publication date: November 8, 2012
    Inventors: Steven T. Mayer, Vijay Bhaskaran, Evan E. Patton, Robert L. Jackson, Jonathan Reid
  • Patent number: 8168540
    Abstract: Apparatus and methods for depositing copper on tungsten are presented. The invention finds particular use in the semiconductor industry for depositing copper seed layers onto fields or through silicon vias having tungsten barrier layers, both reducing cost and complexity of existing methods.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 1, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan Reid, Sesha Varadarajan, Ugur Emekli
  • Patent number: 8128791
    Abstract: In a copper electroplating apparatus having separate anolyte and catholyte portions, the concentration of anolyte components (e.g., acid or copper salt) is controlled by providing a diluent to the recirculating anolyte. The dosing of the diluent can be controlled by the user and can follow a pre-determined schedule. For example, the schedule may specify the diluent dosing parameters, so as to prevent precipitation of copper salt in the anolyte. Thus, precipitation-induced anode passivation can be minimized.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: March 6, 2012
    Assignee: Novellus Systems, Inc.
    Inventors: Bryan Buckalew, Jonathan Reid, John Sukamto, Zhian He, Seshasayee Varadarajan, Steven T. Mayer
  • Patent number: 8076241
    Abstract: Methods are provided for multi-step Cu metal plating on a continuous Ru metal film in recessed features found in advanced integrated circuits. The use of a continuous Ru metal film prevents formation of undesirable micro-voids during Cu metal filling of high-aspect-ratio recessed features, such as trenches and vias, and enables formation of large Cu metal grains that include a continuous Cu metal layer plated onto the continuous Ru metal film. The large Cu grains lower the electrical resistivity of the Cu filled recessed features and increase the reliability of the integrated circuit.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: December 13, 2011
    Assignees: Tokyo Electron Limited, Novellus Systems, Inc.
    Inventors: Frank M. Cerio, Jr., Shigeru Mizuno, Jonathan Reid, Thomas Ponnuswamy
  • Patent number: 8048280
    Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: November 1, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Vijay Bhaskaran, Evan E. Patton, Robert L. Jackson, Jonathan Reid
  • Publication number: 20110221044
    Abstract: Apparatus and methods for filling through silicon vias (TSV's) with copper having an intervening tungsten layer between the copper plug and the silicon are disclosed. Methods are useful for Damascene processing, with or without a TSV feature. The tungsten layer serves as a diffusion barrier, a seed layer for copper electrofill and a means of reducing CTE-induced stresses between copper and silicon. Adhesion of the tungsten layer to the silicon and of the copper layer to the tungsten is described.
    Type: Application
    Filed: March 12, 2010
    Publication date: September 15, 2011
    Inventors: Michal Danek, Tom Mountsier, Jonathan Reid, Juwen Gao, Aaron Fellis
  • Patent number: 7964506
    Abstract: A two-step semiconductor electroplating process deposits copper onto wafers coated with a semi-noble metal in manner that is uniform across the wafer and free of voids after a post electrofill anneal. A seed-layer plating bath nucleates copper uniformly and conformably at a high density in a very thin film using a unique pulsed waveform. The wafer is then annealed before a second bath fills the features. The seed-layer anneal improves adhesion and stability of the semi-noble to copper interface, and the resulting copper interconnect stays void-free after a post electrofill anneal.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: June 21, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Thomas Ponnuswamy, John Sukamto, Jonathan Reid, Steve Mayer
  • Publication number: 20110076390
    Abstract: Methods are provided for multi-step Cu metal plating on a continuous Ru metal film in recessed features found in advanced integrated circuits. The use of a continuous Ru metal film prevents formation of undesirable micro-voids during Cu metal filling of high-aspect-ratio recessed features, such as trenches and vias, and enables formation of large Cu metal grains that include a continuous Cu metal layer plated onto the continuous Ru metal film. The large Cu grains lower the electrical resistivity of the Cu filled recessed features and increase the reliability of the integrated circuit.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Applicants: TOKYO ELECTRON LIMITED, NOVELLUS SYSTEMS, INC.
    Inventors: Frank M. Cerio, JR., Shigeru Mizuno, Jonathan Reid, Thomas Ponnuswamy
  • Patent number: 7854828
    Abstract: An apparatus for electroplating a layer of metal on the surface of a wafer includes a second cathode located remotely with respect to the wafer. The remotely positioned second cathode allows modulation of current density at the wafer surface during an entire electroplating process. The second cathode diverts a portion of current flow from the near-edge region of the wafer and improves the uniformity of plated layers. The remote position of second cathode allows the insulating shields disposed in the plating bath to shape the current profile experienced by the wafer, and therefore act as a “virtual second cathode”. The second cathode may be positioned outside of the plating vessel and separated from it by a membrane.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: December 21, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan Reid, Seshasayee Varadarajan, Bryan Buckalew, Patrick Breiling, Glenn Ibarreta
  • Patent number: 7799684
    Abstract: A two-step semiconductor electroplating process deposits copper onto wafers coated with a semi-noble metal in manner that is uniform across the wafer and free of voids. A plating bath nucleates copper uniformly and conformably at a high density in a very thin film. A second bath fills the features. A unique pulsed waveform enhances the nucleation density and reduces resistivity of the very thin film deposited in the nucleation operation. The process produces a thinner and conformal copper seed film than traditional PVD copper seed processes.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: September 21, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan Reid, Seyang Park, Seshasayee Varadarajan, Natalia Doubina
  • Publication number: 20100116672
    Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.
    Type: Application
    Filed: June 9, 2009
    Publication date: May 13, 2010
    Applicant: Novellus Systems, Inc.
    Inventors: Steven Mayer, Jingbin Feng, Zhian He, Jonathan Reid, Seshasayee Varadarajan
  • Publication number: 20100044236
    Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.
    Type: Application
    Filed: October 26, 2009
    Publication date: February 25, 2010
    Applicant: NOVELLUS SYSTEMS, INC.
    Inventors: Steven Mayer, Jingbin Feng, Zhian He, Jonathan Reid, Seshasayee Varadarajan
  • Publication number: 20100032310
    Abstract: An apparatus for electroplating a layer of metal on the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer (preferably within 5 mm of the wafer surface) which serves to modulate ionic current at the wafer surface, and a second cathode configured to divert a portion of current from the wafer surface. The ionically resistive ionically permeable element in a preferred embodiment is a disk made of a resistive material having a plurality of perforations formed therein, such that perforations do not form communicating channels within the body of the disk. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.
    Type: Application
    Filed: November 7, 2008
    Publication date: February 11, 2010
    Inventors: Jonathan Reid, Bryan Buckalew, Zhian He, Seyang Park, Seshasayee Varadarajan, Bryan Pennington, Thomas Ponnuswamy, Patrick Breiling, Glenn Ibarreta, Steven Mayer
  • Publication number: 20100032303
    Abstract: An apparatus for electroplating a layer of metal on the surface of a wafer includes a second cathode located remotely with respect to the wafer. The remotely positioned second cathode allows modulation of current density at the wafer surface during an entire electroplating process. The second cathode diverts a portion of current flow from the near-edge region of the wafer and improves the uniformity of plated layers. The remote position of second cathode allows the insulating shields disposed in the plating bath to shape the current profile experienced by the wafer, and therefore act as a “virtual second cathode”. The second cathode may be positioned outside of the plating vessel and separated from it by a membrane.
    Type: Application
    Filed: August 16, 2006
    Publication date: February 11, 2010
    Inventors: Jonathan Reid, Seshasayee Varadarajan, Bryan Buckalew, Patrick Breiling, Glenn Ibarreta
  • Patent number: D670396
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: November 6, 2012
    Inventor: Jonathan Reid Doogan