Patents by Inventor Jonathan Reid

Jonathan Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7378413
    Abstract: A pyrimidone derivative represented by formula (I) or a salt thereof: Wherein: R1 represents a hydrogen atom or a C1-6 alkyl group which may be substituted by a C6,10 aryl group; R2 represents a C1-10 alkyl group which may be substituted, a C2-6 alkenyl group which may be substituted, a C3-6 alkynyl group which may be substituted, a C3-6 cycloalkyl group which may be substituted, or a C6-10 ARYL group which may be substituted; or R1 and R2 form together a C2-6 alkylene group which may be substituted; or R1 and R2 form together a chain of formula —(CH2)2—X—(CH2)2— or —(CH2)2—X—(CH2)3— where X represents a oxygen atom, a sulfur atom, or a nitrogen atom which may be substituted; R3 represents a 2, 3 or 4-pyridyl group optionally substituted by a C1-4 alkyl group, C1-4 alkoxy group or halogen atom; and R4 represents a C1-10 alkyl group optionally substituted by a hydroxyl group, amino, C1-6 monoalkylamino group, C2-12 dialkylamino group or C6,10 aryl group which may be substituted.
    Type: Grant
    Filed: January 13, 2005
    Date of Patent: May 27, 2008
    Assignees: Sanofi Aventis, Mitsubishi Pharma Corporation
    Inventors: Antonio Almario Carcia, Ryoichi Ando, Keiichi Arimoto, Fumiaki Uehara, Adrien Tak Li, Aya Shoda, Jonathan Reid Frost, Kazutoshi Watanabe
  • Patent number: 7211175
    Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan Reid, Robert Contolini
  • Publication number: 20060011483
    Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.
    Type: Application
    Filed: September 16, 2005
    Publication date: January 19, 2006
    Inventors: Steven Mayer, Vijay Bhaskaran, Evan Patton, Robert Jackson, Jonathan Reid
  • Patent number: 6946065
    Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: September 20, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Vijay Bhaskaran, Evan E. Patton, Robert L. Jackson, Jonathan Reid
  • Publication number: 20050098440
    Abstract: Methods are provided for electrochemically depositing copper on a work piece. One method includes the step of depositing overlying the work piece a barrier layer having a surface and subjecting the barrier layer surface to a surface treatment adapted to facilitate deposition of copper on the barrier layer. Copper then is electrochemically deposited overlying the barrier layer.
    Type: Application
    Filed: November 10, 2003
    Publication date: May 12, 2005
    Inventors: Sridhar Kailasam, John Drewery, Jonathan Reid, Eric Webb, Johanes Sukamto
  • Patent number: 6844335
    Abstract: A pyrimidone derivative represented by formula (I) or a salt thereof: Wherein: R1 represents a hydrogen atom or a C1-6 alkyl group which may be substituted by a C6,10 aryl group; R2 represents a C1-10 alkyl group which may be substituted, a C2-6 alkenyl group which may be substituted, a C3-6 alkynyl group which may be substituted, a C3-6 cycloalkyl group which may be substituted, or a C6-10 ARYL group which may be substituted; or R1 and R2 form together a C2-6 alkylene group which may be substituted; or R1 and R2 form together a chain of formula —(CH2)2—X—(CH2)2— or —(CH2)2—X—(CH2)3— where X represents a oxygen atom, a sulfur atom, or a nitrogen atom which may be substituted; R3 represents a 2, 3 or 4-pyridyl group optionally substituted by a C1-4 alkyl group, C1-4 alkoxy group or halogen atom; and R4 represents a C1-10 alkyl group optionally substituted by a hydroxyl group, amino, C1-6 monoalkylamino group, C2-12 dialkylamino group or C6,10 aryl group which may be substituted.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: January 18, 2005
    Assignees: Sanofi-Synthelabo, Mitsubishi Pharma Corporation
    Inventors: Antonio Almario Garcia, Ryoichi Ando, Keiichi Arimoto, Fumiaki Uehara, Adrien Tak Li, Aya Shoda, Jonathan Reid Frost, Kazutoshi Watanabe
  • Publication number: 20030187004
    Abstract: A pyrimidone derivative represented by formula (I) or a salt thereof: 1
    Type: Application
    Filed: December 2, 2002
    Publication date: October 2, 2003
    Inventors: Antonio Almario Garcia, Ryoichi Ando, Keiichi Arimoto, Fumiaki Uehara, Adrien Tak Li, Aya Shoda, Jonathan Reid Frost, Kazutoshi Watanabe
  • Patent number: 6562204
    Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: May 13, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan Reid, Robert Contolini
  • Patent number: 6551483
    Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: April 22, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan Reid, Robert Contolini
  • Patent number: 6471845
    Abstract: A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: October 29, 2002
    Assignees: International Business Machines Corporation, Novellus Systems, Inc.
    Inventors: John O. Dukovic, William E. Corbin, Jr., Erick G. Walton, Peter S. Locke, Panayotis C. Andricacos, James E. Fluegel, Evan Patton, Jonathan Reid
  • Patent number: 6193859
    Abstract: An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: February 27, 2001
    Assignees: Novellus Systems, Inc., International Business Machines Corporation
    Inventors: Robert J. Contolini, Jonathan Reid, Evan Patton, Jingbin Feng, Steve Taatjes, John Owen Dukovic
  • Patent number: 6159354
    Abstract: An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: December 12, 2000
    Assignees: Novellus Systems, Inc., International Business Machines, Inc.
    Inventors: Robert J. Contolini, Jonathan Reid, Evan Patton, Jingbin Feng, Steve Taatjes, John Owen Dukovic