Abstract: Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.

Abstract: Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.

Abstract: Methods, systems, and devices for queue management for a memory system are described. The memory system may include a first decoder associated with a first error control capability and a second decoder associated with a second error control capability. The memory system may receive a command and identify an expected latency for performing an error control operation on the command. The memory system may determine whether to assign the command to a first queue associated with the first decoder or a second queue associated with the second decoder based at least in part on the expected latency for processing the command using the first decoder. Upon assigning the command to a decoder, the command may be processed by the first queue or the second queue.

Abstract: Methods, systems, and devices for topology-based retirement in a memory system are described. In some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. For example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.

Abstract: Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

Abstract: Methods, systems, and devices for write booster pinning are described. In some examples, a memory device may receive one or more commands (e.g., write commands) while operating in a first mode (e.g., a write booster mode). Some write commands may include an indication to pin the data to one or more SLCs. For example, a first write command may be associated with first data and a first indicator and a second write command may be associated with second data. Both the first data and the second data may be written to one or more SLCs. When maintenance operations are performed on the SLCs, the second data may be moved (e.g., written) to one or more MLCs. Additionally or alternatively, the memory system may receive one or more commands to unpin data (e.g., the first data) such that it may be moved to one or more MLCs during subsequent maintenance operations.

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.

Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

Abstract: A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data. A flush command is received from a host system. A cached data item is retrieved from a volatile memory. The cached data item and at least a subset of the valid data stored at the victim MU are written to a target MU.

Abstract: A method includes determining a logical saturation of a memory device in a memory sub-system and adjusting a code rate of the memory device based on the logical saturation, wherein the code rate represents a ratio of user data to a combination of the user data and error correction data.

Abstract: A method includes receiving a request to perform a memory access operation, wherein the memory access operation includes a set of sub-operations, selecting a current quantization data structure from a plurality of current quantization data structures, wherein each current quantization data structure of the plurality of current quantization data structures maintains, for each sub-operation of the set of sub-operations, a respective current quantization value reflecting an amount of current that is consumed by the respective sub-operation based on a set of peak power management (PPM) operation parameters, and causing the memory access operation to be performed using PPM based on the current quantization data structure.

Abstract: A memory device includes memory dies. Each memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations for implementing peak power management (PPM) data burst communication. The operations include monitoring a data burst with respect to the memory array, detecting a current reservation trigger associated with the data burst, in response detecting the current reservation trigger, reserving an initial amount of current reflecting a maximum current consumption value associated with a maximum data transfer speed of the data burst, detecting a plurality of input/output cycles of the data burst following the preamble period, and in response to detecting the number of input/output cycles, reserving, based on an analysis of the plurality of input/output cycles, a subsequent amount of current reflecting an actual current consumption value associated with an actual data transfer speed of the data burst.

Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.

Abstract: A memory die includes a memory array and control logic, operatively coupled with the memory array, to perform operations including receiving a peak power management (PPM) token during a current PPM cycle, in response to receiving the PPM token, determining, based on a set of communication frequencies, whether to communicate auxiliary data to at least one other memory die during the current PPM cycle, wherein each communication frequency of the set of communication frequencies indicates when a respective type of auxiliary data is eligible for communication during a PPM cycle, and in response to determining to communicate auxiliary data to the at least one other memory die, causing a selected type of auxiliary data to be communicated to the at least one other memory die, wherein the selected type of auxiliary data is determined from the set of communication frequencies in view of the current PPM cycle.

Abstract: Methods, systems, and devices for compression and decompression of trim data are described. A memory system may store one or more trim settings to a volatile memory in a compressed manner, and may expand (e.g., decompress) the data as part of a write operation to a non-volatile memory (e.g., during a start-up procedure). For example, compressed (e.g., non-expanded) data including trim settings may be stored to a volatile memory, and a portion of the array of volatile memory cells may be temporarily allocated to expand the data (e.g., copy the data, invert the data, copy the inverted data). Once the data is expanded, it may be stored in the non-volatile memory, and the temporarily allocated portion of the array of volatile memory cells may be reallocated (e.g., allocated for another purpose). The expanded data may include multiple copies and inverted copies of the trim settings.

Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

Abstract: Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Methods, systems, and devices for queue management for a memory system are described. The memory system may include a first decoder associated with a first error control capability and a second decoder associated with a second error control capability. The memory system may receive a command and identify an expected latency for performing an error control operation on the command. The memory system may determine whether to assign the command to a first queue associated with the first decoder or a second queue associated with the second decoder based at least in part on the expected latency for processing the command using the first decoder. Upon assigning the command to a decoder, the command may be processed by the first queue or the second queue.