Abstract: Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

Abstract: Methods, systems, and devices for communication of power parameters between a power management integrated circuit (PMIC) and a memory system are described. According to techniques described herein, a memory system transmit a power request directly to a PMIC. The memory system may transmit the power request in response to one or more parameters satisfying corresponding threshold values, in response to a query from the PMIC, or both. The PMIC may update a power mode of the PMIC and output a power to the memory system according to the power request. The PMIC may transmit a confirmation to the memory system in response to the received request, and the memory system may begin operating in accordance with the requested power in response to receiving the confirmation. In some cases, the memory system may send the power request over an inter-integrated circuit (I2C) channel or one or more pins.

Abstract: Methods, systems, and devices for efficient data management for memory system error handling are described. If a new data transfer is desired between the controller and a memory device when the latches are full, the controller may obtain data that has been loaded in one of the latches, temporarily store that data in a buffer, and overwrite the latch with the new data associated with the new data transfer. After the controller is finished working with the new data now stored in the latch, the controller may restore the data from the buffer to the latch so the prior data transfer may continue. This may prevent loss of data or reduce the quantity of data that is temporarily lost from latches and needs to be re-transferred when the latches are full.

Abstract: Processing logic maintains a data item tag hierarchy in view of user context information and identifies, from the data item tag hierarchy, a highest ranked data item tag of a plurality of data item tags associated with a data item, the plurality of data item tags representing a content of the data item. The processing logic further storing the data item on a memory device at a first shared storage location together with one or more additional data items with which the highest ranked data item tag is also associated.

Abstract: Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

Abstract: Methods, systems, and devices for power arbitration for systems of electronic components. A system may include a power source, a signaling conductor coupled with a voltage source, and a set of electronic components. One or more of the electronic components may include respective circuitry coupled with the power source and a respective switching component (e.g., a transistor) coupled with the signaling conductor. In some implementations, an electronic component of the set may be configured to determine an operation of its respective circuitry that is associated with a power consumption from the power source. Based on such a determination, the electronic component may switch its respective switching component in accordance with an identifier associated with the electronic component, and determine whether to perform the operation based on monitoring a signal level of the signaling conductor during the switching.

Abstract: Methods, systems, and devices for memory write performance techniques are described. A memory system may receive a sequence of commands, for example from a host system. Based on a relationship between logical block addresses of the sequence of commands, the memory system may delay performing a memory management operation (e.g., a garbage collection procedure, a power operation, a cache synchronization operation, a data relocation operation, or the like) for a duration. For example, the memory system may determine whether a quantity of write commands in the sequence that include non-consecutive logical block addresses exceeds a threshold. In some cases, the memory system may perform one or more commands in the sequence during the duration. Subsequently (e.g., at the end of the duration), the memory system may perform the memory management operation.

Abstract: A memory system may receive an indication that a low-power mode associated with the memory system has been activated, and a voltage supplied to the memory system may be altered as a result of the low-power mode being activated. In accordance with receiving the indication, the memory system may perform one or more operations to extend a duration after the voltage is altered during which a voltage applied to the volatile memory device remains above a threshold voltage associated with retaining data stored in the volatile memory device.

Abstract: Methods, systems, and devices for physical prefetch are described. A memory system may prefetch data from physical addresses that are sequential to a physical address that has recently been read by the memory system. For example, the memory system may determine that a rate of access for a virtual block exceeds a threshold, and the memory system may prefetch the physically sequential data in response to the rate of access exceeding the threshold. In some examples, the memory system may receive a command to read a logical block address corresponding to a first physical address. The memory system may determine that the rate of access to the virtual block exceeds the threshold. The memory system may identify one or more second physical addresses that are sequential to the first physical address, and the memory system may transfer data from the one or more second physical addresses to a buffer.

Abstract: Methods, systems, and devices for power supply for low power modes in memory are described. A memory system may include one or more memory devices, a controller, a first voltage source associated with a first supply rail, and a second voltage source associated with a second supply rail. During an active mode, a memory device may be coupled with the first voltage source and the first supply rail. In some examples, the controller may send a command to the memory device to enter a low power mode, or to couple with the second voltage source, after which the memory device may couple one or more components with the second supply rail and the second voltage source. Additionally, or alternatively, the one or more components may be coupled with the second voltage source in response to a voltage of the first voltage source failing to satisfy a threshold.

Abstract: Methods, systems, and devices for transfer command power gating within a memory system are described. A memory device may dynamically activate data path circuitry within the memory device according to an operation to be performed at the memory device. In response to receiving signaling that indicates a transfer of data stored in the memory device, the memory device may generate a power gating signal associated with activation of the data path circuitry. The signaling may include a command from a controller before a data transfer, a preamble associated with the data transfer, or both. The memory device may transfer the data via the data path using the activated data path circuitry in response to the signaling. The memory device may receive second signaling to deactivate the data path circuitry after the data transfer is complete to reduce power consumption and improve performance.

Abstract: A system includes a memory device having a memory array with memory cells organized into memory blocks, and a processing device coupled to the memory device. The processing device receives a programming command directed to a set of memory cells, the programming command associated with a cell type indicating a number of bits to be stored per memory cell. The processing device determines, based on the cell type, an erase mode corresponding to the cell type, and determines whether a memory block is in an erased state corresponding to the erase mode. Responsive to determining that the memory block is in the erased state corresponding to the erase mode, the processing device performs a programming operation with respect to the set of memory cells. Responsive to determining that the memory block is not in the erased state corresponding to the erase mode, the processing device erases the memory block in the erase mode prior to performing the programming operation.

Abstract: Processing logic receives an indication of at least one of content preferences or contextual information associated with a request to view a media content stream and controls one or more parameters of the media content stream according to the at least one of the content preferences or contextual information to create a personalized media content stream. The processing logic further provides the personalized media content stream to a user device.

Abstract: Methods, systems, and devices for power management associated with memory and a controller are described. A memory system performs a power management operation that accounts for power usage by any combination of application specific integrated circuits (ASICs) and memory arrays. The power management operation includes multiple logical unit numbers (LUNs) assigned to a single ASIC, which increases a quantity of bits for communicating a power usage. An ASIC included in a memory system may utilize twice as many bits for communicating power usage information when compared to a NAND array. As part of the power management operation, an ASIC may transmit, to a controller, a first set of bits indicating a power usage of the ASIC, a first subset of the set of bits transmitted during a first instance of a token ring and a second subset of the set of bits transmitted during a second instance of the token ring.

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

Abstract: Methods, systems, and devices to enhance read performance for memory data word decoding using power allocation based on error pattern detection in both QLC and TLC in both QLC and TLC products are described. A plurality of data words may be processed using a first decoder engine of a decoder of a memory device according to a first power setting. The decoder may detect a pattern of errors in the plurality of data words. The decoder may further communicate a status signal based on detecting the pattern of errors. The resource manager may allocate based on the status signal, a second amount of power credits to the decoder. The decoder may process a portion of the plurality of data words using a second decoder engine according to the second amount of power credits.

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

Abstract: Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

Abstract: Processing logic maintains a data item tag hierarchy in view of user context information and identifies, from the data item tag hierarchy, a highest ranked data item tag of a plurality of data item tags associated with a data item, the plurality of data item tags representing a content of the data item. The processing logic further storing the data item on a memory device at a first shared storage location together with one or more additional data items with which the highest ranked data item tag is also associated.