Abstract: Disclosed are methods of RNA-triggered protein cleavage by the CRISPR Cas7-11-Csx29 complex. A guide RNA specifically hybridizes to a RNA target, and Csx29 cleaves Csx30 when Cas7-11:Csx29 complex binds to the target RNA.

Abstract: Disclosed herein are sample dishes for use with microscopes that are simple to mount on a microscope and facilitate easy manipulation of tissue samples disposed thereon during imaging as well as methods of their use. A sample dish comprises an optical interface and, optionally, a support member that holds the optical interface. The optical interface of a sample dish is suitably transparent and planar such that a focal plane of a microscope can reside uniformly at or within a surface of a sample during imaging. In certain embodiments, a support member comprises a dish for holding excess fluid. In certain embodiments, a sample dish comprises separation ribs. In certain embodiments, a sample dish comprises one or more manipulation members (e.g., tabs). In certain embodiments, a sample dish is used with an imaging artifact reducing fluid.

Abstract: A photosensitive flexographic printing form, and process for manufacturing the same. The printing form includes a base, a first series of relief patterns having a first elevation with respect to the base in an image area of the base, and a second series of relief patterns having one or more elevations lower than the first elevation and located outside of the image area.

Abstract: A photosensitive flexographic printing form, and process for manufacturing the same. The printing form includes a base, a first series of relief patterns having a first elevation with respect to the base in an image area of the base, and a second series of relief patterns having one or more elevations lower than the first elevation and located outside of the image area.

Abstract: A non-volatile memory cell, having an antifuse for storing data, is disclosed for use in a non-volatile data storage device. The non-volatile memory cell includes multiple redundant signal pathways to provide redundant access to the antifuse. During operation, the non-volatile memory cell can access the antifuse using a first signal pathway from among the multiple redundant signal pathways. However, when the first signal pathway is inoperable, the non-volatile memory cell is able to access the antifuse using a second signal pathway from among the multiple redundant signal pathways. The non-volatile memory cell is fabricated using a continuous region of one or more diffusion layers to allow efficient connection to other non-volatile memory cells to form an array of memory cells for the non-volatile data storage device.

Abstract: The present invention relates to a method for assisting an excavator operator with the loading of a mobile transportation implement, in particular heavy-duty truck, by means of the excavator shovel, wherein a loading strategy with the number of excavator loading cycles to be executed for loading the transportation implement is proposed to the excavator operator via an assistance system and/or the current payload distribution on the loading area of the transportation implement is indicated.

Abstract: A non-volatile memory cell, having an antifuse for storing data, is disclosed for use in a non-volatile data storage device. The non-volatile memory cell includes multiple redundant signal pathways to provide redundant access to the antifuse. During operation, the non-volatile memory cell can access the antifuse using a first signal pathway from among the multiple redundant signal pathways. However, when the first signal pathway is inoperable, the non-volatile memory cell is able to access the antifuse using a second signal pathway from among the multiple redundant signal pathways. The non-volatile memory cell is fabricated using a continuous region of one or more diffusion layers to allow efficient connection to other non-volatile memory cells to form an array of memory cells for the non-volatile data storage device.

Abstract: A differential bit cell includes two memory elements that are configured to have different states. Each of the two memory elements is connected to a respective switching element. Each of these switching elements may have process variances, which may result in a degradation of read and/or write margins. To mitigate the effect of such variances, another switching element is coupled to the two memory elements and their respective switching elements in a manner that couples the aforementioned switching elements in a parallel fashion. In this way, the mismatch effects between the switching elements can be negated during read operations. During programming operations, such a configuration allows for the programming of both memory elements to different states with a single current pulse and also reduces the effective resistance of the programming path.

Abstract: A bitcell may include an insulating region, a first doping proximate to the insulating region, and a second doping surrounding the first doping. The second doping can be characterized by a higher gate voltage breakdown than the first doping. Also, the bitcell may include a gate terminal, and the bitcell may be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating region between the gate terminal and the first doping.

Abstract: A programmable memory cell including a thick oxide spacer transistor, a programmable thin oxide anti-fuse disposed adjacent to the thick oxide spacer transistor, and first and second thick oxide access transistors. The thick oxide spacer transistor and first and second thick oxide access transistors can include an oxide layer that is thicker than an oxide layer of the programmable thin oxide anti-fuse. The programmable thin oxide anti-fuse and the thick oxide spacer transistor can be natively doped. The first and second thick oxide access transistors can be doped so as to have standard threshold voltage characteristics.

Abstract: A differential bit cell includes two memory elements that are configured to have different states. Each of the two memory elements is connected to a respective switching element. Each of these switching elements may have process variances, which may result in a degradation of read and/or write margins. To mitigate the effect of such variances, another switching element is coupled to the two memory elements and their respective switching elements in a manner that couples the aforementioned switching elements in a parallel fashion. In this way, the mismatch effects between the switching elements can be negated during read operations. During programming operations, such a configuration allows for the programming of both memory elements to different states with a single current pulse and also reduces the effective resistance of the programming path.

Abstract: A bitcell may include an insulating region, a first doping proximate to the insulating region, and a second doping surrounding the first doping. The second doping can be characterized by a higher gate voltage breakdown than the first doping. Also, the bitcell may include a gate terminal, and the bitcell may be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating region between the gate terminal and the first doping.

Abstract: A bitcell can include an insulating area, a first doping, a second doping, and a gate terminal for the insulating area. The second doping can be proximate to the first doping and proximate to the insulating area. The second doping can be characterized by a lower threshold voltage than the first doping. The bitcell can be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating area between the gate terminal and the first doping.

Abstract: A programmable memory cell including a thick oxide spacer transistor, a programmable thin oxide anti-fuse disposed adjacent to the thick oxide spacer transistor, and first and second thick oxide access transistors. The thick oxide spacer transistor and first and second thick oxide access transistors can include an oxide layer that is thicker than an oxide layer of the programmable thin oxide anti-fuse. The programmable thin oxide anti-fuse and the thick oxide spacer transistor can be natively doped. The first and second thick oxide access transistors can be doped so as to have standard threshold voltage characteristics.

Abstract: A bitcell can include an insulating area, a first doping, a second doping, and a gate terminal for the insulating area. The second doping can be proximate to the first doping and proximate to the insulating area. The second doping can be characterized by a lower threshold voltage than the first doping. The bitcell can be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating area between the gate terminal and the first doping.

Abstract: A memory device includes an antifuse. The antifuse is configured to program a bit cell of the memory device. The antifuse is configured with a PMOS device.

Abstract: A delay locked loop generates a voltage on a common node as a function of a phase difference between a reference input and a feedback input. A first voltage-controlled delay line coupled between the reference input and the feedback input and has a first delay, which is controlled by the voltage on the common node. A second voltage-controlled delay line is selectively coupled in series with the first delay line, between the reference input and the feedback input, as a function of a test control input. The second delay line has a second delay, which is controlled by the voltage on the common node.

Abstract: A memory device includes an antifuse. The antifuse is configured to program a bit cell of the memory device.

Abstract: A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor couples the antifuse to the read circuit. The read circuit and the isolation transistor have different power domains.

Abstract: Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal of the bitcells, where the programming burns a conductive hole in an oxide layer above a higher threshold voltage layer in a memory device. The bitcells may comprise an oxide layer and a doped channel, which may comprise a plurality of different threshold voltage layers. The plurality of different threshold voltage layers may comprise at least one layer with a higher threshold voltage and at least one layer with a lower threshold voltage. The oxide may comprise a gate oxide. The bitcell may comprise an anti-fuse device. The layer with a higher threshold voltage may be separated from an output terminal of the bitcell by the at least one layer with a lower threshold voltage.