Abstract: Methods and systems for split threshold voltage programmable bitcells are disclosed and may include selectively programming bitcells in a memory device by applying a high voltage to a gate terminal of the bitcells, where the programming burns a conductive hole in an oxide layer above a higher threshold voltage layer in a memory device. The bitcells may comprise an oxide layer and a doped channel, which may comprise a plurality of different threshold voltage layers. The plurality of different threshold voltage layers may comprise at least one layer with a higher threshold voltage and at least one layer with a lower threshold voltage. The oxide may comprise a gate oxide. The bitcell may comprise an anti-fuse device. The layer with a higher threshold voltage may be separated from an output terminal of the bitcell by the at least one layer with a lower threshold voltage.

Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.

Abstract: A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse.

Abstract: A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage.

Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.

Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.

Abstract: A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell.

Abstract: A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage.

Abstract: A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse.

Abstract: A differential latch-based one time programmable memory cell is provided. The differential latch-based one time programmable memory cell includes a differential latching amplifier having a first set of fuse devices coupled to the first input and a second set of fuse devices coupled to the second input. Only one set of fuse devices can be programmed in a memory cell. If one or more fuse devices in a set of fuse devices are programmed, the side having the programmed fuse will present a lower voltage at its input to the differential latching amplifier. Differential latching amplifier outputs a “0” or a “1” depending on the side having the programmed fuse.

Abstract: A quad SRAM based one time programmable memory cell is provided. Prior to programming, the memory cell operates as an SRAM memory cell. After programming, the memory cell operates as a one-time programmable non-volatile memory cell. The memory cell includes a storage element coupled at a first side to a first upper fuse and a first lower fuse and coupled at a second side to a second upper fuse and a second lower fuse. When the first upper fuse and second lower fuse are programmed, the storage element outputs a first value. When the second upper fuse and first lower fuse are programmed, the storage element outputs a second value. After programming the upper fuse acts as a pull-up fuse and the lower fuse acts as a pull-down fuse hold the state of the cell.

Abstract: A one-time programmable memory. The one-time programmable memory has an antifuse and a read circuit configured to read the antifuse. An isolation transistor couples the antifuse to the read circuit. The read circuit and the isolation transistor have different power domains.

Abstract: The present invention provides a system and method for monitoring a short clock cycle on a semiconductor chip. The system includes a phase-locked loop (PLL) for receiving a reference clock as input and for outputting a PLL clock out. The system includes a delay-locked loop (DLL) for receiving the PLL clock out as input and for outputting a DLL phase offset clock. The DLL is locked to a frequency of the PLL clock out. The system may include an edge comparator for receiving the PLL clock out and the DLL phase offset clock as input. The edge comparator is suitable for monitoring each edge of the PLL clock out and each edge of the DLL phase offset clock, and for reporting a short clock cycle when an edge of the PLL clock out comes before an edge of the DLL phase offset clock.

Abstract: A delay locked loop generates a voltage on a common node as a function of a phase difference between a reference input and a feedback input. A first voltage-controlled delay line coupled between the reference input and the feedback input and has a first delay, which is controlled by the voltage on the common node. A second voltage-controlled delay line is selectively coupled in series with the first delay line, between the reference input and the feedback input, as a function of a test control input. The second delay line has a second delay, which is controlled by the voltage on the common node.

Abstract: A phase-locked loop within an integrated circuit assembly is provided. The phase-locked loop includes a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly. One or more metal layers are formed over and interconnect the plurality of semiconductor devices in a metallization pattern. The phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.

Abstract: A phase-locked loop within an integrated circuit assembly is provided. The phase-locked loop includes a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly. One or more metal layers are formed over and interconnect the plurality of semiconductor devices in a metallization pattern. The phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.

Abstract: A method of power sequence protection for a level shifter is disclosed that includes the steps of placing the level shifter in a pre-selected state if an input voltage supply is not powered on when an output voltage supply is powered on and releasing the level shifter from the pre-selected state to follow transitions of an input signal when the input voltage supply is powered on.

Abstract: An apparatus comprising a plurality of serially coupled delay cells configured to generate an output signal having a frequency varied in response to a control signal. Each of the delay cells may be configured to generate one or more intermediate signals in response to the control signal and present the intermediate signals to a next of the delay cells. One or more next to the last of the intermediate signals may be fed back to a first of the delay cells. One or more last of the intermediate signals may be presented as the output signal.

Abstract: An apparatus comprising a plurality of serially coupled delay cells configured to generate an output signal having a frequency varied in response to a control signal. Each of the delay cells may be configured to generate one or more intermediate signals in response to the control signal and present the intermediate signals to a next of the delay cells. One or more next to the last of the intermediate signals may be fed back to a first of the delay cells. One or more last of the intermediate signals may be presented as the output signal.

Abstract: An integrated circuit having input output buffers, where the integrated circuit is powered by at least a core power supply and an input output power supply. A level shifter receives an active low signal that indicates that the core power supply has powered down. The level shifter then outputs a known state upon receipt of the active low signal. A control circuit receives the known state form the level shifter, and then tristates the input output buffers upon receipt of the known state.