Abstract: A method of processing network traffic within a computing system, comprises at a first configurable logic device (CLD), receiving an ingress network packet from an external network interface, associating the ingress network packet with a timestamp indicating the time of receipt, parsing the ingress network packet to locate a link-layer checksum value and a routing-layer checksum value, determining whether the link-layer and routing-layer checksum values are correct based on the ingress network packet contents, and transmitting the ingress network packet to a second CLD via a high-speed interconnection; and at the second CLD receiving the ingress network packet, parsing the ingress network packet to locate a source address and a destination address, determining a destination and a route for the ingress network packet based at least in part on the source and destination addresses, and transmitting the ingress network packet to the determined destination via the determined route.

Abstract: A system for programming one or more configurable logic devices (e.g., FPGA or CPLD) via universal serial bus (USB) may include one or more CLDs; a microcontroller coupled to the one or more CLDs via a parallel data bus; a processor coupled to the microcontroller via a USB interface, the processor having access to CLD access logic and one or more CLD images; and instructions executable by the processor to program at least one of the CLDs by loading the CLD access logic onto the microcontroller, using the CLD access logic loaded on the microcontroller to set each of the at least one CLD to a programming mode, and forwarding a particular CLD image from the processor to the microcontroller via the USB interface and from the microcontroller to each of the at least one CLD via the parallel data bus.

Abstract: A method for booting devices in a multi-card computing system comprising a plurality of cards connected to a shared backplane may include: dynamically generating a Media Access Control (MAC) addresses for at least some of the devices in the computing system, the dynamically generated MAC address for each device including information regarding the location of that device within the multi-card computing system; a boot management system receiving a boot-related information request from a particular device in the multi-card system, the boot-related information request comprising a request for particular boot-related information for facilitating a boot process for the requesting device, and including the MAC address of the requesting device; and the boot management system determining whether to send a response to the requesting device with the requested boot-related information based at least on the information in the MAC address regarding the location of the requesting device within the multi-card computing syste

Abstract: A method of routing internal network traffic within a computing system comprises receiving a network packet at a configurable logic device (CLD), parsing the network packet to obtain a destination address, searching a predetermined range of a routing table wherein each row of the routing table specifies a range of possible destination addresses and routing information, identifying a matching row of the routing table wherein the destination address falls within the range of possible destination addresses of the matching row, and routing the packet according to the routing information.

Abstract: A method for managing the capture of packets in a computing system comprises maintaining a buffer tail pointer in a memory of an instruction executing device, receiving a series of packets at an instruction executing device, for each received packet prepending a header comprising a packet length and a packet pointer set to a current value of the buffer tail pointer, determining a next free memory location by adding the current value of the buffer tail pointer to the length of a previous packet identified by the buffer tail pointer, temporarily writing the packet and prepend header to the next free memory location in a circular packet buffer in a memory coupled to the instruction executing device, and setting the buffer tail pointer to the next free memory location.

Abstract: A method of sending programming and debug commands, comprises loading control instructions on a processor from an attached tangible, non-transitory computer-readable medium, copying the contents of a program image file by the processor from the computer-readable medium across a bus to a programmable device on the same card as the processor, signaling the programmable device to send an instruction to a configurable logic device (CLD) on the same card as the processor via a debug channel.

Abstract: A method offloading data intensive tasks from a processor comprises receiving at a configurable logic device (CLD) a network packet, parsing the network packet to determine that the packet is a TCP segment, searching a partially assembled packet table to locate an associated partially assembled packet data structure, inserting the network packet into the associated partially assembled packet data structure, recognizing that the partially assembled packet data structure contains every segment produced from an original TCP packet, assembling a fully assembled TCP packet from the data in the partially assembled packet data structure, and transmitting the fully assembled TCP packet to a processor in the same computer system as the CLD.

Abstract: A method of routing internal network traffic within a computing system, comprises receiving a network packet at a configurable logic device (CLD), parsing the network packet to obtain a source address and a destination address, searching a predetermined range of a routing table wherein each row of the routing table specifies a range of possible destination addresses and a thread group identifier, identifying a matching row of the routing table wherein the destination address falls within the range of possible destination addresses of the matching row, calculating a hash value based at least in part on the source and destination addresses, and determining a thread identifier based at least in part on the hash value and the thread group identifier.

Abstract: A method of initializing programmable devices on a shared bus, comprises, on power up, loading control instructions on a processor from an attached tangible, non-transient computer-readable medium, automatically allowing a first programmable device on a common bus to exit its reset state and enter a read-to-program state as the computer system powers up, automatically holding a second programmable device on the common bus in its reset state, querying the common bus by the processor to identify the first programmable device, copying the contents of a program image file by the processor from the computer-readable medium across the common bus to the first programmable device, and once the first programmable device has been programmed with the contents of the program image file, signaling the first programmable device to release the reset hold on the second programmable device.

Abstract: A method for distributing packets across multiple parallel interfaces between a first instruction executing device and a second instruction executing device may include: the first instruction executing device receiving a stream of data packets, each data packet including header information regarding that data packet; and for each data packet, the first instruction executing device executing instructions to identify one or more particular information elements in the data packet; execute a hash function to the one or more particular information elements to calculate a hash value for the data packet; select a particular one of the multiple parallel communication interfaces based on the calculated hash value for the data packet; and forward the data packet to the second instruction executing device via the selected communication interface. Such method may provide traffic load balancing across the multiple parallel interfaces.

Abstract: A method of flexibly binding physical network interface ports to a processor in a network testing system comprises generating an egress network packet with a prepend header at a processor, wherein the prepend header specifies a particular physical network interface through which the egress network packet should be transmitted, transmitting the prepended network packet to a configurable logic device (CLD), routing the prepended network packet to the specified physical network interface.

Abstract: A method for managing the capture of packets in a computing system comprises maintaining a buffer tail pointer in a memory of an instruction executing device, receiving a series of packets at an instruction executing device, for each received packet prepending a header comprising a packet length and a packet pointer set to a current value of the buffer tail pointer, determining a next free memory location by adding the current value of the buffer tail pointer to the length of a previous packet identified by the buffer tail pointer, temporarily writing the packet and prepend header to the next free memory location in a circular packet buffer in a memory coupled to the instruction executing device, and setting the buffer tail pointer to the next free memory location

Abstract: A method offloading data intensive tasks from a processor comprises receiving at a configurable logic device (CLD) a network packet, parsing the network packet to determine that the packet is a TCP segment, searching a partially assembled packet table to locate an associated partially assembled packet data structure, inserting the network packet into the associated partially assembled packet data structure, recognizing that the partially assembled packet data structure contains every segment produced from an original TCP packet, assembling a fully assembled TCP packet from the data in the partially assembled packet data structure, and transmitting the fully assembled TCP packet to a processor in the same computer system as the CLD.

Abstract: A method of routing internal network traffic within a computing system, comprises receiving a network packet at a configurable logic device (CLD), parsing the network packet to obtain a source address and a destination address, searching a predetermined range of a routing table wherein each row of the routing table specifies a range of possible destination addresses and a thread group identifier, identifying a matching row of the routing table wherein the destination address falls within the range of possible destination addresses of the matching row, calculating a hash value based at least in part on the source and destination addresses, and determining a thread identifier based at least in part on the hash value and the thread group identifier.

Abstract: A system for programming one or more configurable logic devices (e.g., FPGA or CPLD) via universal serial bus (USB) may include one or more CLDs; a microcontroller coupled to the one or more CLDs via a parallel data bus; a processor coupled to the microcontroller via a USB interface, the processor having access to CLD access logic and one or more CLD images; and instructions executable by the processor to program at least one of the CLDs by loading the CLD access logic onto the microcontroller, using the CLD access logic loaded on the microcontroller to set each of the at least one CLD to a programming mode, and forwarding a particular CLD image from the processor to the microcontroller via the USB interface and from the microcontroller to each of the at least one CLD via the parallel data bus.

Abstract: A method of communicating between devices within a card in a computing system comprises sending a command network packet from a first instruction executing device to a second instruction executing device via an Ethernet network, wherein the command network packet contains an instruction to be executed on the second instruction executing device, and receiving a responsive network packet sent from the second instruction executing device to the first instruction executing device via the Ethernet network, wherein the responsive network packet indicates a result of the instruction.

Abstract: A method of sending programming and debug commands, comprises loading control instructions on a processor from an attached tangible, non-transitory computer-readable medium, copying the contents of a program image file by the processor from the computer-readable medium across a bus to a programmable device on the same card as the processor, signaling the programmable device to send an instruction to a configurable logic device (CLD) on the same card as the processor via a debug channel.

Abstract: A method for processing data packets in a computer system may include receiving a data packet at a configurable logic device (e.g., an FPGA), each packet including header information regarding the data packet, the configurable logic device automatically identifying particular information elements in the header information of the data packet, the configurable logic device automatically executing a hash function programmed on the configurable logic device to calculate a hash value for the data packet based on the particular information elements, and processing the data packet based on the calculated hash value for the data packet. The calculate hash value may be used for various purposes, e.g., routing and/or load balancing of traffic across multiple interfaces. The configurable logic device may be able to execute the hash function at line rate, thus freeing up processor cycles in one or more related processors.

Abstract: A method of routing internal network traffic within a computing system comprises receiving a network packet at a configurable logic device (CLD), parsing the network packet to obtain a destination address, searching a predetermined range of a routing table wherein each row of the routing table specifies a range of possible destination addresses and routing information, identifying a matching row of the routing table wherein the destination address falls within the range of possible destination addresses of the matching row, and routing the packet according to the routing information.

Abstract: A method of processing network traffic within a computing system, comprises at a first configurable logic device (CLD), receiving an ingress network packet from an external network interface, associating the ingress network packet with a timestamp indicating the time of receipt, parsing the ingress network packet to locate a link-layer checksum value and a routing-layer checksum value, determining whether the link-layer and routing-layer checksum values are correct based on the ingress network packet contents, and transmitting the ingress network packet to a second CLD via a high-speed interconnection; and at the second CLD receiving the ingress network packet, parsing the ingress network packet to locate a source address and a destination address, determining a destination and a route for the ingress network packet based at least in part on the source and destination addresses, and transmitting the ingress network packet to the determined destination via the determined route.