Abstract: A method for processing data packets in a computer system may include receiving a data packet at a configurable logic device (e.g., an FPGA), each packet including header information regarding the data packet, the configurable logic device automatically identifying particular information elements in the header information of the data packet, the configurable logic device automatically executing a hash function programmed on the configurable logic device to calculate a hash value for the data packet based on the particular information elements, and processing the data packet based on the calculated hash value for the data packet. The calculate hash value may be used for various purposes, e.g., routing and/or load balancing of traffic across multiple interfaces. The configurable logic device may be able to execute the hash function at line rate, thus freeing up processor cycles in one or more related processors.

Abstract: A method of sending programming and debug commands, comprises loading control instructions on a processor from an attached tangible, non-transitory computer-readable medium, copying the contents of a program image file by the processor from the computer-readable medium across a bus to a programmable device on the same card as the processor, signaling the programmable device to send an instruction to a configurable logic device (CLD) on the same card as the processor via a debug channel.

Abstract: A method of initializing programmable devices on a shared bus, comprises, on power up, loading control instructions on a processor from an attached tangible, non-transient computer-readable medium, automatically allowing a first programmable device on a common bus to exit its reset state and enter a read-to-program state as the computer system powers up, automatically holding a second programmable device on the common bus in its reset state, querying the common bus by the processor to identify the first programmable device, copying the contents of a program image file by the processor from the computer-readable medium across the common bus to the first programmable device, and once the first programmable device has been programmed with the contents of the program image file, signaling the first programmable device to release the reset hold on the second programmable device.

Abstract: A method offloading data intensive tasks from a processor comprises receiving at a configurable logic device (CLD) a network packet, parsing the network packet to determine that the packet is a TCP segment, searching a partially assembled packet table to locate an associated partially assembled packet data structure, inserting the network packet into the associated partially assembled packet data structure, recognizing that the partially assembled packet data structure contains every segment produced from an original TCP packet, assembling a fully assembled TCP packet from the data in the partially assembled packet data structure, and transmitting the fully assembled TCP packet to a processor in the same computer system as the CLD.

Abstract: A method for managing the capture of packets in a computing system comprises maintaining a buffer tail pointer in a memory of an instruction executing device, receiving a series of packets at an instruction executing device, for each received packet prepending a header comprising a packet length and a packet pointer set to a current value of the buffer tail pointer, determining a next free memory location by adding the current value of the buffer tail pointer to the length of a previous packet identified by the buffer tail pointer, temporarily writing the packet and prepend header to the next free memory location in a circular packet buffer in a memory coupled to the instruction executing device, and setting the buffer tail pointer to the next free memory location