Abstract: A memory cell and method of fabricating the memory cell includes an insulating layer formed on a first electrode layer, the insulating layer having a first opening, a stencil layer formed on the insulating layer, and having a second opening formed in an area of the first opening, a phase-change material layer formed on a surface of the first electrode layer in the first opening, and an electrically conductive layer including a first portion formed on the stencil layer and defining a second electrode layer and a second portion formed on the phase-change material layer.

Abstract: A method of tuning a high temperature superconductor (HTS) resonator includes the steps of providing a HTS inductor and a HTS capacitor, the HTS capacitor being electrically connected to the HTS inductor. A tuning body is provided adjacent to the HTS inductor and the HTS capacitor. The relative position of the tuning body with respect to the HTS inductor and the HTS capacitor is altered so as to tune the resonator. A tunable resonant circuit is provided that includes a substrate having a planar surface. At least one resonator formed from HTS material is disposed on the substrate, the resonator having one or more turns that when combined, turn through greater than 360°.

Abstract: A memory cell and method of fabricating the memory cell includes an insulating layer formed on a first electrode layer, the insulating layer having a first opening, a stencil layer formed on the insulating layer, and having a second opening formed in an area of the first opening, a phase-change material layer formed on a surface of the first electrode layer in the first opening, and an electrically conductive layer including a first portion formed on the stencil layer and defining a second electrode layer and a second portion formed on the phase-change material layer.

Abstract: A magnetic memory element switchable by current injection includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers (e.g., between two of the magnetic layers). The memory element has the switching threshold current and device impedance suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuits.