Abstract: A method is used to configure an extended analog computer for use as an application controller. The method includes selecting input pins from among a plurality of pins in a continuous sheet processor, selecting an arrangement of intermediate and output pins from among the remaining pins in the plurality of pins in the continuous sheet processor, applying a pattern data set to the input pins, using an evolutionary algorithm, coupling current sources and sinks to the intermediate and output pins, measuring an error between an output and its expected value, and continuing to select intermediate and output pin arrangements, apply pattern data sets, and measure errors until a configuration threshold is met.

Abstract: A method is used to configure an extended analog computer for use as an application controller. The method includes selecting input pins from among a plurality of pins in a continuous sheet processor, selecting an arrangement of intermediate and output pins from among the remaining pins in the plurality of pins in the continuous sheet processor, applying a pattern data set to the input pins, using an evolutionary algorithm, coupling current sources and sinks to the intermediate and output pins, measuring an error between an output and its expected value, and continuing to select intermediate and output pin arrangements, apply pattern data sets, and measure errors until a configuration threshold is met.

Abstract: A one-diode circuit for negated implication (.about..fwdarw.) is derived from a 12-transistor Lukasiewicz implication circuit (.fwdarw.). The derivation also yields an adjustable three-transistor implication circuit with maximum error less than 1% of full scale. Two Lukasiewicz logic arrays (.English Pound.LAs) are proposed that use area-efficient implementations of the one-diode and three-transistor implication circuits. The very dense diode-tower .English Pound.LA contains 36,000 implications in an area that previously held 92 implications; the three-transistor .English Pound.LA contains 1,990 implications. Both .English Pound.LAs double the number of inputs per pin on the IC package. Very dense .English Pound.LAs make .English Pound.LA-based fuzzy controllers and neural networks practical. As an example, an .English Pound.LA retina that detects edges in 15 nanoseconds is described.

Abstract: A one-diode circuit for negated implication (.about..fwdarw.) is derived from a 12-transistor Lukasiewicz implication circuit (.fwdarw.). The derivation also yields an adjustable three-transistor implication circuit with maximum error less than 1% of full scale. Two Lukasiewicz logic arrays (.English Pound.LAs) are proposed that use area-efficient implementations of the one-diode and three-transistor implication circuits. The very dense diode-tower .English Pound.LA contains 36,000 implications in an area that previously held 92 implications; the three-transistor .English Pound.LA contains 1,990 implications. Both .English Pound.LAs double the number of inputs per pin on the IC package. Very dense .English Pound.LAs make .English Pound.LA-based fuzzy controllers and neural networks practical. As an example, an .English Pound.LA retina that detects edges in 15 nanoseconds is described.

Abstract: A LOW RISC (reduced instruction set computer) III microprocessor reduces the number of branches taken during execution of logic, functional, and symbolic programs to increase the efficiency and effectiveness of pipelined execution memory interleave, and reduces the complexity of RISC architectures. The LOW RISC III is a 40-bit, 4-stage pipelined processor which is pipelined with each stage operating synchronously in parallel. Pipeline breaks are reduced by moving partial unification and trail checking into hardware, and eliminating many short branches by conditional execution of the various instructions.