Area-efficient implication circuits for very dense Lukasiewicz logic arrays
A one-diode circuit for negated implication (.about..fwdarw.) is derived from a 12-transistor Lukasiewicz implication circuit (.fwdarw.). The derivation also yields an adjustable three-transistor implication circuit with maximum error less than 1% of full scale. Two Lukasiewicz logic arrays (.English Pound.LAs) are proposed that use area-efficient implementations of the one-diode and three-transistor implication circuits. The very dense diode-tower .English Pound.LA contains 36,000 implications in an area that previously held 92 implications; the three-transistor .English Pound.LA contains 1,990 implications. Both .English Pound.LAs double the number of inputs per pin on the IC package. Very dense .English Pound.LAs make .English Pound.LA-based fuzzy controllers and neural networks practical. As an example, an .English Pound.LA retina that detects edges in 15 nanoseconds is described.
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Claims
1. A negated implication analog logic circuit comprising:
- a first diode having an anode defining a first circuit input and a cathode;
- a second diode having an anode connected to said cathode of said first diode and defining a circuit output thereat, and a cathode defining a second circuit input;
- a first composite analog signal applied to said first circuit input, said first composite analog signal including a first number of having continuous values within a first specified range analog signals; and
- a second composite analog signal applied to said second circuit input, said second composite analog signal including a second number of having continuous values within a second specified range analog signals, the circuit producing a negated implication analog logic signal at said circuit output in response to said first and second composite analog signals.
2. The circuit of claim 1 wherein said first and second composite analog signals are analog current signals.
3. The circuit of claim 1 wherein said first and second diodes form at least a portion of an integrated circuit.
4. The circuit of claim 1 wherein said first and second diodes are each schottky diodes.
5. The circuit of claim 1 wherein said first number of continuously variable analog signals is equal to said second number of continuously variable analog signals.
6. A negated implication analog logic circuit comprising:
- a first diode having an anode adapted to receive a first number of having continuous values within a first specified range analog signals, and a cathode; and
- a second diode having an anode connected to said cathode of said first diode and defining a circuit output thereat, and a cathode adapted to receive a second number of analog signals having continuous values within a second specified range;
- wherein the circuit is responsive to said first and second numbers of continuously variable analog signals to produce a negated implication analog logic signal at said circuit output.
7. The circuit of claim 6 wherein said first and second composite analog signals are analog current signals.
8. The circuit of claim 6 wherein said first and second diodes form at least a portion of an integrated circuit.
9. The circuit of claim 6 wherein said first and second diodes are each schottky diodes.
10. The circuit of claim 6 wherein said first number of continuously variable analog signals is equal to said second number of continuously variable analog signals.
| 3097311 | July 1963 | Tiemann |
| 3116426 | December 1963 | Oshima et al. |
| 3124708 | March 1964 | Reinecke, Jr. et al. |
| 3239687 | March 1966 | Steele |
| 4694418 | September 15, 1987 | Ueno |
Type: Grant
Filed: Mar 25, 1998
Date of Patent: Jun 29, 1999
Assignee: Indiana University (Bloomington, IN)
Inventor: Jonathan W. Mills (Bloomington, IN)
Primary Examiner: Terry D. Cunningham
Law Firm: Beck, Michael & Beck, P.C.
Application Number: 9/47,753
International Classification: H03K 1900;
