Patents by Inventor Jong-bom Seo
Jong-bom Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230292496Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Inventors: CHANG MU AN, SANG YEOL KANG, YOUNG-LIM PARK, JONG-BOM SEO, SE HYOUNG AHN
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Patent number: 11711915Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.Type: GrantFiled: January 7, 2022Date of Patent: July 25, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Chang Mu An, Sang Yeol Kang, Young-Lim Park, Jong-Bom Seo, Se Hyoung Ahn
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Patent number: 11488958Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode being electrically connected to the landing pad, a dielectric layer on the lower electrode, the dielectric layer extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode and including first fluorine (F) therein, wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the upper plate electrode includes a portion in which a concentration of the first fluorine decreases as a distance from the interface of the upper plate electrode increases.Type: GrantFiled: June 30, 2020Date of Patent: November 1, 2022Inventors: Chang Mu An, Sang Yeol Kang, Young-Lim Park, Jong-Bom Seo, Se Hyoung Ahn
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Publication number: 20220130835Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.Type: ApplicationFiled: January 7, 2022Publication date: April 28, 2022Inventors: CHANG MU AN, SANG YEOL KANG, YOUNG-LIM PARK, JONG-BOM SEO, SE HYOUNG AHN
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Patent number: 11244946Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.Type: GrantFiled: June 24, 2020Date of Patent: February 8, 2022Inventors: Chang Mu An, Sang Yeol Kang, Young-Lim Park, Jong-Bom Seo, Se Hyoung Ahn
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Patent number: 11233118Abstract: An integrated circuit (IC) device includes an electrode, a dielectric layer facing the electrode, and a plurality of interface layers interposed between the electrode and the dielectric layer and including a first metal. The plurality of interface layers includes a first interface layer and a second interface layer. An oxygen content of the first interface layer is different from an oxygen content of the second interface layer.Type: GrantFiled: May 1, 2019Date of Patent: January 25, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Lim Park, Sun-Min Moon, Chang-Hwa Jung, Young-Geun Park, Jong-Bom Seo, Kyu-Ho Cho
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Publication number: 20210125996Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.Type: ApplicationFiled: June 24, 2020Publication date: April 29, 2021Inventors: CHANG MU AN, SANG YEOL KANG, YOUNG-LIM PARK, JONG-BOM SEO, SE HYOUNG AHN
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Publication number: 20210125993Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode being electrically connected to the landing pad, a dielectric layer on the lower electrode, the dielectric layer extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode and including first fluorine (F) therein, wherein the upper plate electrode includes an interface facing the upper electrode, and wherein the upper plate electrode includes a portion in which a concentration of the first fluorine decreases as a distance from the interface of the upper plate electrode increases.Type: ApplicationFiled: June 30, 2020Publication date: April 29, 2021Inventors: Chang Mu An, Sang Yeol Kang, Young-Lim Park, Jong-Bom Seo, Se Hyoung Ahn
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Patent number: 10825893Abstract: A semiconductor device includes a first electrode on a substrate, a second electrode on the substrate, a dielectric layer structure between the first electrode and the second electrode, and a crystallization inducing layer between the dielectric layer structure and the first electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a second dielectric layer on the first dielectric layer and including a second dielectric material.Type: GrantFiled: June 8, 2018Date of Patent: November 3, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-ho Cho, Sang-yeol Kang, Sun-min Moon, Young-lim Park, Jong-bom Seo
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Patent number: 10658454Abstract: A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the second electrode, and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a tetragonal crystal structure. The seed layer includes a seed material that satisfies at least one of a lattice constant condition or a bond length condition.Type: GrantFiled: September 17, 2019Date of Patent: May 19, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyuho Cho, Sangyeol Kang, Suhwan Kim, Sunmin Moon, Young-Lim Park, Jong-Bom Seo, Joohyun Jeon
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Publication number: 20200013853Abstract: A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the second electrode, and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a tetragonal crystal structure. The seed layer includes a seed material that satisfies at least one of a lattice constant condition or a bond length condition.Type: ApplicationFiled: September 17, 2019Publication date: January 9, 2020Inventors: Kyuho CHO, Sangyeol KANG, Suhwan KIM, Sunmin MOON, Young-Lim PARK, Jong-Bom SEO, Joohyun JEON
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Publication number: 20190355804Abstract: An integrated circuit (IC) device includes an electrode, a dielectric layer facing the electrode, and a plurality of interface layers interposed between the electrode and the dielectric layer and including a first metal. The plurality of interface layers includes a first interface layer and a second interface layer. An oxygen content of the first interface layer is different from an oxygen content of the second interface layer.Type: ApplicationFiled: May 1, 2019Publication date: November 21, 2019Inventors: YOUNG-LIM PARK, SUN-MIN MOON, CHANG-HWA JUNG, YOUNG-GEUN PARK, JONG-BOM SEO, KYU-HO CHO
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Patent number: 10453913Abstract: A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the second electrode, and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a tetragonal crystal structure. The seed layer includes a seed material that satisfies at least one of a lattice constant condition or a bond length condition.Type: GrantFiled: March 28, 2018Date of Patent: October 22, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyuho Cho, Sangyeol Kang, Suhwan Kim, Sunmin Moon, Young-Lim Park, Jong-Bom Seo, Joohyun Jeon
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Publication number: 20180315811Abstract: A capacitor includes a first electrode and a second electrode spaced apart from each other, a dielectric layer disposed between the first electrode and the second electrode, and a seed layer disposed between the first electrode and the dielectric layer. The dielectric layer includes a dielectric material having a tetragonal crystal structure. The seed layer includes a seed material that satisfies at least one of a lattice constant condition or a bond length condition.Type: ApplicationFiled: March 28, 2018Publication date: November 1, 2018Inventors: Kyuho CHO, SANGYEOL KANG, SUHWAN KIM, Sunmin MOON, Young-Lim PARK, Jong-Bom SEO, Joohyun JEON
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Patent number: 9893142Abstract: A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film.Type: GrantFiled: March 29, 2016Date of Patent: February 13, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Se-Hyoung Ahn, Young-Geun Park, Jong-Bom Seo, Jae-Hyoung Choi
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Publication number: 20170018604Abstract: A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film.Type: ApplicationFiled: March 29, 2016Publication date: January 19, 2017Inventors: Se-Hyoung AHN, Young-Geun PARK, Jong-Bom SEO, Jae-Hyoung CHOI
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Patent number: 9496328Abstract: A method of manufacturing a capacitor for a semiconductor device includes forming a lower electrode, forming a dielectric layer on the lower electrode, forming a first upper electrode on the dielectric layer, adsorbing an organic silicon source onto a surface of the first upper electrode, and forming a second upper electrode on the first upper electrode onto which the organic silicon source is adsorbed. Related devices and fabrication methods are also discussed.Type: GrantFiled: April 9, 2015Date of Patent: November 15, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jong Bom Seo, Young Geun Park, Bong Hyun Kim, Sun Ho Kim, Hyun Jun Kim, Se Hyoung Ahn, Chang Mu An
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Patent number: 9431476Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.Type: GrantFiled: March 31, 2016Date of Patent: August 30, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
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Publication number: 20160225845Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.Type: ApplicationFiled: March 31, 2016Publication date: August 4, 2016Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
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Patent number: 9330960Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.Type: GrantFiled: June 5, 2014Date of Patent: May 3, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee