Patents by Inventor Jong-bom Seo

Jong-bom Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9287270
    Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: March 15, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Hwan Oh, Hyun-Jun Kim, Jong-Bom Seo, Ki-Vin Im, Han-Jin Lim
  • Publication number: 20160043163
    Abstract: A method of manufacturing a capacitor for a semiconductor device includes forming a lower electrode, forming a dielectric layer on the lower electrode, forming a first upper electrode on the dielectric layer, adsorbing an organic silicon source onto a surface of the first upper electrode, and forming a second upper electrode on the first upper electrode onto which the organic silicon source is adsorbed. Related devices and fabrication methods are also discussed.
    Type: Application
    Filed: April 9, 2015
    Publication date: February 11, 2016
    Inventors: Jong Bom Seo, Young Geun Park, Bong Hyun Kim, Sun Ho Kim, Hyun Jun Kim, Se Hyoung Ahn, Chang Mu An
  • Publication number: 20150091069
    Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer.
    Type: Application
    Filed: May 15, 2014
    Publication date: April 2, 2015
    Inventors: Jung-Hwan OH, Hyun-Jun KIM, Jong-Bom SEO, Ki-Vin IM, Han-Jin LIM
  • Publication number: 20140361403
    Abstract: A semiconductor device includes a first capacitor structure, a second capacitor structure, and an insulation pattern. The first capacitor structure includes a first lower electrode, a first dielectric layer and a first upper electrode sequentially stacked on a substrate. The second capacitor structure includes a second lower electrode, a second dielectric layer and a second upper electrode sequentially stacked on the substrate, and is adjacent to the first capacitor structure. The insulation pattern partially fills a space between the first and second capacitor structures, and an air gap is formed between the first and second capacitor structures on the insulation pattern.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 11, 2014
    Inventors: Young-Seung Cho, Sung-Eui Kim, Ji-Young Kim, Hoon Jeong, Chan-Won Kim, Jong-Bom Seo, Seung-Jun Lee, Jun-Soo Lee
  • Publication number: 20120100687
    Abstract: Example embodiments relate to methods for fabricating a capacitor and methods for fabricating a semiconductor device including the capacitor. The methods for fabricating a capacitor may include forming a preliminary lower electrode with a first area on a substrate; implanting ions in the preliminary lower electrode to form a lower electrode with a second area that is larger or substantially larger than the first area; and forming a dielectric layer and an upper electrode on the lower electrode.
    Type: Application
    Filed: October 17, 2011
    Publication date: April 26, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hanjin Lim, Jong-Bom Seo, Seokwoo Nam, Bonghyun Kim, Yongjae Lee, KiVin Im
  • Publication number: 20110222207
    Abstract: In a method of forming a dielectric layer structure, a precursor thin film chemisorbed on a substrate in a process chamber is formed using a source gas including a metal precursor. The process chamber is purged and pumped out to remove a remaining source gas therein and to remove any metal precursor physisorbed on the precursor thin film. The forming of the precursor thin film and the purging and pumping out of the process chamber are alternately and repeatedly performed to form a multi-layer precursor thin film. An oxidant is provided onto the multilayer precursor thin film to form a bulk oxide layer.
    Type: Application
    Filed: March 14, 2011
    Publication date: September 15, 2011
    Inventors: Tae-Jong Lee, Jae-Young Park, Jong-Bom Seo, Seok-Woo Nam, Bong-Hyun Kim, Han-Jin Lim, Seung-Sik Chung
  • Publication number: 20100112777
    Abstract: A method of forming a semiconductor device includes forming a bottom electrode having a top surface and a side surface on a semiconductor substrate, performing a tilted ion implantation process to supply ions to the top surface of the bottom electrode and to a portion of the side surface of the bottom electrode, and forming a dielectric layer on the bottom electrode. The formation of the dielectric layer is delayed at the ion-supplied top surface of the bottom electrode and the ion-supplied portion of the side surface of the bottom electrode.
    Type: Application
    Filed: November 4, 2009
    Publication date: May 6, 2010
    Inventors: HanJin LIM, Seokwoo Nam, Junghee Chung, KyoungRyul Yoon, Jong-Bom Seo, Jun-Noh Lee, Sunghoon Bae
  • Patent number: 7425761
    Abstract: A method of manufacturing a dielectric layer for a capacitor including sequentially supplying and purging a first and a second precursor material for a first and a second predetermined amount of time, respectively, in an initial cycle, sequentially supplying and purging the first and the second precursor materials for a third predetermined amount of time, which is shorter than the first and/or second predetermined amount of time, in a post cycle, which follows the initial cycle, and repeating the initial and post cycles to form a dielectric layer having a predetermined thickness.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: September 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-hyoung Choi, Sung-ho Kang, Jung-hee Chung, Seog-min Lee, Jong-bom Seo, Young-min Kim
  • Publication number: 20080054400
    Abstract: Example embodiments relate to a capacitor including p-type doped silicon germanium and a method of manufacturing the capacitor. The capacitor may include a lower electrode, a dielectric layer, an upper electrode, a barrier layer and a capping layer. The lower electrode may have a cylindrical shape. The dielectric layer may be on the lower electrode. The dielectric layer may have a uniform thickness. The upper electrode may be on the dielectric layer. The upper electrode may have a more uniform thickness. The capping layer may be on the upper electrode. The capping layer may include a silicon germanium layer doped with p-type impurities. The barrier layer may be between the upper electrode and the capping layer to prevent (or reduce) the p-type impurities from infiltrating into the dielectric layer.
    Type: Application
    Filed: July 26, 2007
    Publication date: March 6, 2008
    Inventors: Woo-Sung Lee, Hong-Bum Park, Hyun-Jin Shin, Jong-Bom Seo
  • Publication number: 20070099379
    Abstract: A method of manufacturing a dielectric layer for a capacitor including sequentially supplying and purging a first and a second precursor material for a first and a second predetermined amount of time, respectively, in an initial cycle, sequentially supplying and purging the first and the second precursor materials for a third predetermined amount of time, which is shorter than the first and/or second predetermined amount of time, in a post cycle, which follows the initial cycle, and repeating the initial and post cycles to form a dielectric layer having a predetermined thickness.
    Type: Application
    Filed: October 10, 2006
    Publication date: May 3, 2007
    Inventors: Jae-hyoung Choi, Sung-ho Kang, Jung-hee Chung, Seog-min Lee, Jong-bom Seo, Young-min Kim