Abstract: A battery module includes battery cells stacked with each other, a pair of end plates provided at both ends of the battery cells in the stacking direction of the battery cells, and a fastening unit fastened to the pair of end plates along the stacking direction and configured to press the pair of end plates along the stacking direction.

Abstract: A battery pack includes a battery module; a processor having a corner formed by two side plates and an opening at the corner, wherein the processor is electrically connected to the battery module and controls charge/discharge of the battery module; and a corner cover which is coupled to the corner and covers the opening.

Abstract: A substrate treating apparatus includes a housing, treating space and support unit to support a substrate, dielectric plate, gas supply unit, and plasma source to generate a plasma and including a top edge electrode above the edge region supported by the support unit and bottom edge electrode below the edge region supported by the support unit, which includes a support plate having an inner space and vacuum hole that communicates with the inner space and sucking the substrate on the top surface. A lift pin assembly can transfer the substrate between an outside transfer unit and the support plate. A decompression unit can apply negative pressure to the inner space. The lift pin assembly includes a base plate and through hole penetrating the base plate to provide negative pressure in a region under the base plate to a region over the base plate. Lift pins protrude from the base plate and support a bottom substrate surface. A driver can lift/lower the base plate within the inner space.

Abstract: A battery pack includes a plurality of cell module assemblies having at least one battery cell, and a control module electrically connected to the plurality of cell module assemblies to manage the plurality of cell module assemblies as at least two groups.

Abstract: A battery pack includes a battery module having at least one battery cell, a pack case configured to accommodate the battery module, and a connection guide unit provided on at least one side of the pack case and configured to be accessible to electrical members of two or more connection types.

Abstract: A battery pack includes a first battery module having a first corner formed by two side plates; a processing unit having a second corner formed by two side plates, electrically connected to the first battery module and controlling charge/discharge of the battery module; and a first coupling member having one side fastened to the first corner and the other side fastened to the second corner.

Abstract: The battery pack includes a battery module; a processing unit which is electrically connected to the battery module and configured to control charge/discharge of the battery module, wherein at least one of the battery module or the processing unit is configured to allow another battery module or another processing unit to be coupled to two or more sides thereof.

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract: In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.

Abstract: In a program method for a multi-level phase change memory device, multi-level data to be programmed in a selected memory cell is received, and a program signal is applied to the selected memory cell according to the received multi-level data. Herein, a rising time of the program signal is set to be longer than a falling time of the program signal.

Abstract: In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.

Abstract: A nano imprint apparatus comprising: a nano imprint template; and a deformation correction unit arranged on the nano imprint template to correct deformation of the nano imprint template.

Abstract: Provided is a phase-change memory device including a phase-change material pattern of which strips are shared by neighboring cells. The phase-change memory device includes a plurality of bottom electrodes arranged in a matrix array. The phase-change material pattern is formed on the bottom electrodes, and the strips of the phase-change material pattern are electrically connected to the bottom electrodes. Each strip of the phase-change material pattern is connected to at least two diagonally neighboring bottom electrodes of the bottom electrodes.

Abstract: A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane.

Abstract: Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating layer. The phase change pattern contacts a top of the first plug electrode and a first potion of a top of the second plug electrode. An interconnection is electrically connected to a second portion of the top of the second plug electrode.

Abstract: In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer is etched to be a first insulating layer pattern having a first opening exposing the first pad. A first plug is formed in the first opening. The first insulating layer pattern where the first plug is formed is etched to be a second insulating layer pattern having a second opening exposing the lower electrode. A second plug including a phase-changeable material is formed in the second opening. A conductive wire and an upper electrode are formed on the first plug and the second plug, respectively.

Abstract: In a program method for a multi-level phase change memory device, multi-level data to be programmed in a selected memory cell is received, and a program signal is applied to the selected memory cell according to the received multi-level data. Herein, a rising time of the program signal is set to be longer than a falling time of the program signal.