Patents by Inventor Jong-Chan Shin

Jong-Chan Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080149910
    Abstract: Provided is a phase-change memory device including a phase-change material pattern of which strips are shared by neighboring cells. The phase-change memory device includes a plurality of bottom electrodes arranged in a matrix array. The phase-change material pattern is formed on the bottom electrodes, and the strips of the phase-change material pattern are electrically connected to the bottom electrodes. Each strip of the phase-change material pattern is connected to at least two diagonally neighboring bottom electrodes of the bottom electrodes.
    Type: Application
    Filed: November 16, 2007
    Publication date: June 26, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeong-geun AN, Hideki HORII, Jong-chan SHIN, Dong-ho AHN, Jun-soo BAE
  • Publication number: 20080093590
    Abstract: Provided are a phase change memory device and a method of forming the same. According to the phase change memory, a first plug electrode and a second plug electrode are spaced apart from each other in a mold insulating layer. A phase change pattern is disposed on the mold insulating layer. The phase change pattern contacts a top of the first plug electrode and a first potion of a top of the second plug electrode. An interconnection is electrically connected to a second portion of the top of the second plug electrode.
    Type: Application
    Filed: October 16, 2007
    Publication date: April 24, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-Ho Ahn, Hideki Horii, Jong-Chan Shin, Jun-Soo Bae, Hyeong-Geun An
  • Publication number: 20070243659
    Abstract: In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer is etched to be a first insulating layer pattern having a first opening exposing the first pad. A first plug is formed in the first opening. The first insulating layer pattern where the first plug is formed is etched to be a second insulating layer pattern having a second opening exposing the lower electrode. A second plug including a phase-changeable material is formed in the second opening. A conductive wire and an upper electrode are formed on the first plug and the second plug, respectively.
    Type: Application
    Filed: April 9, 2007
    Publication date: October 18, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-Ju SHIN, Jong-Chan SHIN, Soon-Oh PARK, Hyeong-Geun AN, Han-Bong KO
  • Patent number: 6316358
    Abstract: A method for forming a uniform conductive pattern on an integrated circuit substrate having a step by a single photography process. An exposure mask has a different pattern in accordance with the topology of the integrated circuit substrate. The exposure mask has a increased inter-pattern space at a lower portion of the step and has a reduced inter-pattern space at a upper portion of the step. During the exposure process, a sufficient amount of light is applied to a photoresist layer at the lower portion of the step and an optical amount of light is applied to the photoresist layer at the upper portion of the step. As a result, scum phenomenon at the lower portion of the step can be prevented. Further, overetching of the conductive pattern at the upper portion of the step can be prevented.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: November 13, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Chan Shin