Abstract: A shoe sole includes one or more openings formed in the peripheral portion for receiving one or more light devices. The light device each includes a circuit board received in a casing and having a switch, and one or more light bulbs. One or more batteries are coupled to the light bulbs for energizing the light bulbs. A cap is detachably secured to each of the casings with peripheral flanges or ribs or with threads, and includes a tube for being forced to engage with the switch and to actuate and energize the light bulbs when the cap is depressed.

Abstract: A recycling apparatus comprises a body; a slit on top having a hole on one end; a rear internal pasteurizing mechanism comprising a pulverizing device and a bottom first container; a front internal crushing mechanism comprising two sets of parallel blade wheels and a bottom second container; and a waste storage mechanism comprising a third container, a spring-loaded lever, and a plunger sliding in the third container. In use sequentially insert the needles of the used syringes into the slit with the piston syringe portion of the syringe held on the slit, push the syringes forward to cause the needles to contact the pulverizing device to be ground into powder while being pasteurized, the powder are dropped into the first container, the remained piston syringe portion of each syringe eventually drops into the crushing mechanism through the hole, the dropped piston syringe portion of each syringe is pressed and cut into pieces by the sets of the blade wheels, and the pieces are dropped into the second container.

Abstract: A method for reducing light reflectance in photolithographic manufacturing process is disclosed including providing an inter-metal dielectric (IMD) layer including at least one via opening extending substantially perpendicular to a thickness therethrough, and, conformally forming an anti-reflectance coating (ARC) layer over said IMD layer such that the ARC layer is formed over sidewalls of the at least one via opening to reduce light reflectance.

Abstract: The present invention is a wafer level integrating method for bonding an un-sliced wafer including image sensors and a wafer-sized substrate including optical components thereon. A zeroth order light reflective substrate is provided between the un-sliced wafer and the wafer-sized substrate. The image sensors are either CMOS or CCD image sensors. The wafer-sized substrate is a transparent plate and the optical components thereon include a blazed grating, a two-dimensional microlens array or other optical-functional elements. The wafer-sized substrate is bonded onto the zeroth order light reflective substrate by an appropriate optical adhesive to form a composite substrate. Bonding pads and bumps are provided at corresponding positions on the bonding surface of the un-sliced wafer and the composite substrate respectively so that the composite substrate and the un-sliced wafer can be bonded together through a reflow process.

Abstract: A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate.

Abstract: A recycling apparatus comprises a body; a slit on top having a hole on one end; a rear internal pasteurizing mechanism comprising a pulverizing device and a bottom first container; a front internal crushing mechanism comprising two sets of parallel blade wheels and a bottom second container; and a waste storage mechanism comprising a third container, a spring-loaded lever, and a plunger sliding in the third container. In use sequentially insert the needles of the used syringes into the slit with the piston syringe portion of the syringe held on the slit, push the syringes forward to cause the needles to contact the pulverizing device to be ground into powder while being pasteurized, the powder are dropped into the first container, the remained piston syringe portion of each syringe eventually drops into the crushing mechanism through the hole, the dropped piston syringe portion of each syringe is pressed and cut into pieces by the sets of the blade wheels, and the pieces are dropped into the second container.

Abstract: A ZIF socket includes a base (10), a cover (12) slidably mounted on the base, a plurality of terminals (19) received in the base, a lever (20) driving the cover to move along the base, and a fastening device (14; 16; 17). The fastening device has a securing portion (146; 166; 176) secured to the base, a neck portion (144; 164; 174) movably received in an elongated hole (125) of the cover, and an elongated head portion (143; 163; 173) abutting against a supporting surface (124) of the cover in which the elongated hole is defined, thereby fastening the cover and the base together in a vertical direction.

Abstract: An image sensor apparatus for converting an incident light into electric signal is disclosed. The apparatus has a color separation layer that comprises a body layer for receiving incident light. A surface of the body layer is covered by a two-dimensional microlens array of lenslets, and the other surface of the body layer is covered by a blazed diffraction grating layer. A zeroth-order reflection layer is disposed behind the color separation layer along the path of the incident light for reflecting away zeroth-order component of the incident light. An image sensor array is disposed further behind the zeroth-order reflection layer along the path of the incident light and comprises a two-dimensional array of light-sensing cells.

Abstract: The invention is an easy-to-assemble LED display driven by a simple circuit for any graphics and text by utilizing a plurality of LED display elements with built-in resistors directly installed on a display with power to light up the LED elements and display texts or graphics. This invention, in particular, allows the user compose different texts or graphics by arranging at will the positions of the LED display elements with built-in resistors on a specific circuit.

Abstract: A vertical memory device on a silicon semiconductor substrate is formed by the following steps. Form an array of isolation silicon oxide structures on the surface of the silicon semiconductor substrate. Form a floating gate trench in the silicon semiconductor substrate between the silicon oxide structures in the array, the trench having trench sidewall surfaces. Dope the sidewalls of the floating gate trench with a threshold implant through the trench sidewall surfaces. Form a tunnel oxide layer on the trench sidewall surfaces, the tunnel oxide layer having an outer surface. Form a floating gate electrode in the trench on the outer surface of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode. Form an interelectrode dielectric layer over the top surface of the floating gate electrode. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

Abstract: A reflective-type diffraction grating structure for use in color display devices such as liquid crystal displays (LCDs). It contains: (1) a plurality of micro-lenses each having a smooth top surface and a blazed zig-zag-shaped grating surface at the bottom; (2) an optical coating formed below the zig-zag-shaped grating surface; and (3) a reflective member formed below the optical coating. With the cooperative actions of the zig-zag-shaped grating surface, the optical coating layer, and the reflective member, an incident light, when reflected, is separated into repeated sequences of red, green, and blue color components and a black matrix segregating the red, green, and blue color components. A sequence of micro-light valves are placed in the path of the reflected incident light to block the undesired color components. The reflective-type diffraction grating structure dispenses with the need for the various layers of color filters.

Abstract: A new process is provided whereby LDD regions for HV CMOS devices and for LV CMOS devices are created using one processing sequence. The gate electrodes for both the High Voltage and the Low Voltage devices are created on the surface of a silicon substrate. The High Voltage LDD (HVLDD) is performed self-aligned with the HV CMOS gate electrode, a gate anneal is performed for both the HV and the LV CMOS devices. The Low Voltage LDD (LVLDD) is performed self-aligned with the LV CMOS gate electrodes. The gate electrodes of the CMOS devices are after this completed with the formation of the gate spacers, the source/drain implants and the back-end processing that is required for CMOS devices.

Abstract: A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

Abstract: A method for forming a passivation layer on at least one copper conductive element in a semiconductor structure and the devices formed are described. In the method, after a top surface of a semiconductor device that contains copper conductors embedded in an insulating layer is first planarized by a chemical mechanical polishing method, an etching process is conducted to create a stepped or corrugated surface between the surface of the copper conductor and the surface of the insulating layer, so that when a passivation layer is later deposited on top of the semiconductor structure, the same stepped or corrugated surface is reproduced in the passivation layer and thus providing a mechanical interlock between the passivation layer and the copper conductor for preventing adhesion failure or peeling of the passivation layer from the surface of the semiconductor structure.

Abstract: A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

Abstract: A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate.

Abstract: A flash memory cell and the making thereof is disclosed where the cell has a damascene-like stacked gate. The stacked gate is formed not by blanket depositing a first polysilicon layer and then subtractively etching to form a floating gate followed by the depositing of a second polysilicon layer separated by an intervening inter-gate dielectric layer over the floating gate. On the contrary, a trench is formed in a nitride layer formed over a substrate using a modified damascene process. The first polysilicon layer is conformally deposited into the damascene-like trench to form the floating gate of the disclosed cell. Then, a layer of inter-gate dielectric layer is formed over the first polysilicon layer in the trench, followed by the forming of a second polysilicon layer over the dielectric layer, thus forming the damascene-like stacked gate of this invention.

Abstract: A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.

Abstract: A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate.

Abstract: A method of manufacture of self-aligned floating gate, flash memory device on a semiconductor substrate includes the following steps. Form a blanket silicon oxide layer over the substrate. Form a blanket floating gate conductor layer over the silicon oxide layer. Pattern the blanket silicon oxide layer, the floating gate conductor layer and the substrate in a patterning process with a single floating gate electrode mask forming floating gate electrodes from the floating gate conductor layer and the silicon oxide layer; and simultaneously form trenches in the substrate adjacent to the floating gate electrode and aligned with the floating gate electrodes thereby patterning the active region in the substrate. Form a blanket dielectric layer on the device filling the trenches and planarized with the top surface of the floating gate electrodes. Form an interconductor dielectric layer over the device including the floating gate electrodes. Form a control gate conductor over the interconductor dielectric layer.