Patents by Inventor Jong-Cheol Lee

Jong-Cheol Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140046013
    Abstract: Provided are an organic semiconductor compound, a method for preparing same, a polymer compound having the organic semiconductor compound of the present invention as a monomer, and an organic semiconductor device containing the polymer compound. Said organic semiconductor compound has side chains in the chemical structure thereof, and is highly soluble in a solvent, and therefore the organic semiconductor compound can be effectively used in solution-based processes.
    Type: Application
    Filed: April 26, 2012
    Publication date: February 13, 2014
    Applicant: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Sang Jin Moon, Jong Cheol Lee, Won Suk Shin, Sang Kyu Lee
  • Patent number: 8648111
    Abstract: The present invention provides an N1-2-thiophen-2-ylethyl-N2-substituted biguanide derivative of formula (I) or a pharmaceutically acceptable salt thereof, a method for preparing same, and a pharmaceutical composition comprising same as an active ingredient. The inventive N1-2-thiophen-2-ylethyl-N2-substituted biguanide derivative exhibits improved blood glucose level- and lipid level-lowering effects even with a reduced dosage as compared to conventional drugs, and thus, it is useful for preventing or treating diabetes, metabolic syndromes such as insulin-independent diabetes, obesity and atherosclerosis, or a P53 gene defect-related cancer.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: February 11, 2014
    Assignees: Hanall Biopharma Co., Ltd., Korea Research Institute of Chemical Technology
    Inventors: Sung Wuk Kim, Sung Soo Jun, Hyae Gyeong Cheon, Kwang Rok Kim, Sang Dal Rhee, Won Hoon Jung, Jong Cheol Lee
  • Patent number: 8642647
    Abstract: The present invention provides an N1-benzo[1,3]dioxol-5-ylmethyl-N2-substituted biguanide derivative of formula (I) or a pharmaceutically acceptable salt thereof, a method for preparing same, and a pharmaceutical composition comprising same as an active ingredient. The inventive N1-benzo[1,3]dioxol-5-ylmethyl-N2-substituted biguanide derivative exhibits improved blood glucose level- and lipid level-lowering effects even with a reduced dosage as compared to conventional drugs, and thus, it is useful for preventing or treating diabetes, metabolic syndromes such as insulin-independent diabetes, obesity and atherosclerosis, or a P53 gene defect-related cancer.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: February 4, 2014
    Assignees: Hanall Biopharma Co., Ltd., Korea Research Institute of Chemical Technology
    Inventors: Sung Wuk Kim, Sung Soo Jun, Hyae Gyeong Cheon, Kwang Rok Kim, Sang Dal Rhee, Won Hoon Jung, Jong Cheol Lee
  • Patent number: 8617950
    Abstract: A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong Jin Kuh, Jong Cheol Lee, Yong Suk Tak, Young Sub You, Kyu Ho Cho, Jong Sung Lim
  • Publication number: 20130321740
    Abstract: A curved display apparatus and a multi display system having the same are provided. The curved display apparatus includes a display panel, and a fixation member which fixes the display panel so that the display panel is curved with multiple curvatures.
    Type: Application
    Filed: May 17, 2013
    Publication date: December 5, 2013
    Applicants: Samsung Display Co., Ltd., Samsung Electronics Co., Ltd.
    Inventors: Jun-seok AN, Dong-wook KIM, Sung-hwan KIM, Jee-su PARK, Chan-hong PARK, Byung-kook SIM, Jong-cheol LEE, Cheol-se LEE, Hyeong-sik CHOI, Byung-wook AHN, Cheong-hun LEE
  • Patent number: 8399364
    Abstract: Methods of manufacturing semiconductor devices including multilayer dielectric layers are disclosed. The methods include forming a multilayer dielectric layer including metal atoms and silicon atoms on a semiconductor substrate. The multilayer dielectric layer includes at least two crystalline metal silicate layers having different silicon concentrations. The multilayer dielectric layer may be used, for example, as a dielectric layer for a capacitor, or as a blocking layer for a nonvolatile memory device.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: March 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kil-chul Kim, Jong-cheol Lee, Ki-vin Im, Jae-hyun Yeo
  • Patent number: 8361551
    Abstract: In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second reaction site. A second precursor including a second central atom is then chemisorbed on the second reaction site.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: January 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Cheol Lee, Ki-Yeon Park, Jun-Noh Lee
  • Patent number: 8357593
    Abstract: Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: January 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-chul Kim, Youn-soo Kim, Ki-vin Im, Cha-young Yoo, Jong-cheol Lee, Ki-yeon Park, Hoon-sang Choi, Se-hoon Oh
  • Patent number: 8343844
    Abstract: A method of manufacturing a capacitor of a semiconductor device includes forming a high-k dielectric pattern on a semiconductor substrate, the high-k dielectric pattern having a pillar shape including a hole therein, forming a lower electrode in the hole of the high-k dielectric pattern, locally forming a blocking insulating pattern on an upper surface of the lower electrode, and forming an upper electrode covering the high-k dielectric pattern and the blocking insulating pattern.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wandon Kim, Jong Cheol Lee, Jin Yong Kim, Beom Seok Kim, Yong-Suk Tak, Kyuho Cho, Ohseong Kwon
  • Publication number: 20120305082
    Abstract: The present invention relates to a pyrene-containing conductive polymer represented by formula 1 and an organic solar cell comprising the same as an organic photovoltaic material. The conductive polymer has improved hole mobility as a result of introducing a specific amount of pyrene either into a polymer, which consists only of a donor functional group comprising one or more aromatic monomers, or into a donor-acceptor type polymer comprising a repeating acceptor introduced into a donor functional group. Thus, the conductive polymer can be used as an organic photovoltaic material in organic photodiodes (OPDs), organic light-emitting diodes (OLEDs), organic thin-film transistors (OTFTs), organic solar cells and the like. In addition, an organic solar cell showing high power conversion efficiency (PCE) can be provided using an organic photovoltaic material comprising the pyrene-containing conductive polymer as an electron donor.
    Type: Application
    Filed: October 13, 2010
    Publication date: December 6, 2012
    Applicant: KOREA RESEARCH INSTITUTE OF CHEMICAL TECHNOLOGY
    Inventors: Sang Jin Moon, Jong Cheol Lee, Won Wook So, Won Suk Shin, Sang Kyu Lee, Sung Cheol Yoon, Dohoon Hwang, Chang Jin Lee
  • Patent number: 8314025
    Abstract: A method of forming a semiconductor device includes forming a lower conductive pattern on a substrate, forming an insulating layer over the lower conductive pattern, forming a contact hole through the insulating layer to expose the lower conductive pattern, forming a first spacer along sides of the contact hole, and then forming a contact plug in the contact hole. The contact plug is formed so as to contact the lower conductive pattern.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: November 20, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Il Cho, Nam-Gun Kim, Jong-Cheol Lee
  • Publication number: 20120276721
    Abstract: A method of forming an oxide layer. The method includes: forming a layer of reaction-inhibiting functional groups on a surface of a substrate; forming a layer of precursors of a metal or a semiconductor on the layer of the reaction-inhibiting functional groups; and oxidizing the precursors of the metal or the semiconductor in order to obtain a layer of a metal oxide or a semiconductor oxide. According to the method, an oxide layer having a high thickness uniformity may be formed and a semiconductor device having excellent electrical characteristics may be manufactured.
    Type: Application
    Filed: April 28, 2012
    Publication date: November 1, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suk-jin Chung, Jong-cheol Lee, Youn-soo Kim, Cha-young Yoo, Sang-yeol Kang
  • Publication number: 20120264271
    Abstract: A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode.
    Type: Application
    Filed: April 3, 2012
    Publication date: October 18, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: BONG JIN KUH, JONG-CHEOL LEE, YONG-SUK TAK, YOUNG-SUB YOU, KYU-HO CHO, JONG-SUNG LIM
  • Patent number: 8258064
    Abstract: Methods of forming a metal silicate layer and methods of fabricating a semiconductor device including the metal silicate layer are provided, the methods of forming the metal silicate layer include forming the metal silicate using a plurality of silicon precursors. The silicon precursors are homoleptic silicon precursors in which ligands bound to silicon have the same molecular structure.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: September 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-cheol Lee, Ki-yeon Park, Se-hoon Oh, Youn-soo Kim
  • Publication number: 20120168904
    Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 5, 2012
    Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang
  • Patent number: 8159012
    Abstract: Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: April 17, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-cheol Lee, Jun-noh Lee, Ki-vin Im, Ki-yeon Park, Sung-hae Lee, Sang-yeol Kang
  • Publication number: 20120088360
    Abstract: Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Inventors: Ki-chul Kim, Jong-cheol Lee, Heung-ahn Kwon, Hyun-wook Lee
  • Patent number: 8110473
    Abstract: A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: February 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yeol Kang, Jong-cheol Lee, Ki-vin Lim, Hoon-sang Choi, Eun-ae Chung
  • Patent number: 8104946
    Abstract: A backlight assembly, in which several parts are unified so as to reduce a number of parts used and simplify an assembly process includes lamps emitting light, first lamp sockets, each of which includes a first connection member coupled with one end of each of the lamps so as to be electrically connected to the end of each of the lamps, and a reflection plate to reflect the light emitted from the lamps, and including socket fixing units formed integrally therewith to respectively fix the first lamp sockets. Each of the socket fixing units includes a socket fixing groove formed on a bottom plane of the reflection plate.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: January 31, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Seok An, Jong Cheol Lee, Dae Hyoun Byoun, Tae Jun You
  • Publication number: 20110242727
    Abstract: A capacitor may include a lower electrode structure, a dielectric layer and an upper electrode structure. The lower electrode structure may include a first lower pattern, a first deformation-preventing layer pattern and a second lower pattern. The first lower pattern may have a cylindrical shape. The first deformation-preventing layer pattern may be formed on an inner surface of the first lower pattern. The second lower pattern may be formed on the first deformation-preventing layer pattern. The dielectric layer may be formed on the lower electrode structure. The upper electrode structure may be formed on the dielectric layer. Thus, the capacitor may have a high capacitance and improved electrical characteristics.
    Type: Application
    Filed: March 31, 2011
    Publication date: October 6, 2011
    Inventors: Wan-Don KIM, Beom-Seok Kim, Jong-Cheol Lee, Kyu-Ho Cho, Jin-Yong Kim, Oh-Seong Kwon, Yong-Suk Tak