Abstract: A phase-change random access memory (PRAM) device including a plurality of nanowires and a method of manufacturing the same include: a lower structure including a plurality of contact plugs; the nanowires extending into the contact plugs from surfaces defining a respective terminal end of the contact plugs; and a phase-change layer formed on top of the nanowires. Therefore, a reset or a set current consumed by the PRAM device is significantly reduced.

Abstract: An LCD device with improved an aperture ratio and decreased parasitic capacitance has a passivation layer of an inorganic material and which includes a gate line on a first substrate; a gate insulating layer on an entire surface of the first substrate including the gate line; a data line on the gate insulating layer in perpendicular to the gate line, to define a pixel region; a thin film transistor at a crossing portion of the gate and data lines; a passivation layer on the entire surface of the first substrate including the thin film transistor; a pixel electrode on the passivation layer, for being connected with a drain electrode of the thin film transistor; and a light-shielding metal for receiving a voltage, formed between the data line and the pixel electrode, to prevent a parasitic capacitance between the data line and the pixel electrode.

Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Abstract: Provided are a Schottky barrier tunnel transistor and a method of manufacturing the same that are capable of minimizing leakage current caused by damage to a gate sidewall of the Schottky barrier tunnel transistor using a Schottky tunnel barrier naturally formed at a semiconductor-metal junction as a tunnel barrier. The method includes the steps of: forming a semiconductor channel layer on an insulating substrate; forming a dummy gate on the semiconductor channel layer; forming a source and a drain at both sides of the dummy gate on the insulating substrate; removing the dummy gate; forming an insulating layer on a sidewall from which the dummy gate is removed; and forming an actual gate in a space from which the dummy gate is removed. In manufacturing the Schottky barrier tunnel transistor using the dummy gate, it is possible to form a high-k dielectric gate insulating layer and a metal gate, and stable characteristics in silicidation of the metal layer having very strong reactivity can be obtained.

Abstract: A communication apparatus and a method for supporting carrier sense multiple access/collision detection (CSMA/CD) are disclosed.

Abstract: A method for separating multiple home networks networked in one communication line into each home network is disclosed, which includes the steps of forming home network for networking apparatuses in the house to communicate with one another, setting individual home codes to each apparatus, connecting the home networks formed in a plurality of houses to one another, and forming packet data including the home codes for communicating.

Abstract: A nonvolatile memory device includes a semiconductor substrate, a charge-trap structure disposed on the semiconductor substrate, which includes an insulating film and a plurality of carbon nanocrystals embedded in the insulating film, and a gate disposed on the charge-trap structure. The nonvolatile memory device may exhibit memory hysteresis characteristics with improved reliability.

Abstract: A digital broadcasting system and a data processing method are disclosed. In an aspect of the present invention, the present invention provides a data processing method including receiving a broadcast signal in which main service data and mobile service data are multiplexed, demodulating the received broadcast signal, outputting demodulation time information of a specific position of a broadcast signal frame, and acquiring reference time information contained in the mobile service data frame, setting the reference time information to a system time clock at a specific time based on the demodulation time information and decoding the mobile service data according to the system time clock.

Abstract: The present invention provides a method of scaling a partial area of a main picture, by which the partial area of the main picture can be magnified in a manner of scaling the partial area of the picture displayed on a screen like using a virtual magnifier without employing a separate expensive hardware resource. The present invention comprises a first step of making a main scaler extract image data of the partial area to be scaled from full image data according to prescribed scaling information including magnification/reduction information for the partial area of a display picture, a second step of making a sub-scaler scale the extracted image data of the partial area at a prescribed rate, and a third step of overlaying the scaled image data of the partial area on the full image data provided from the main scaler.

Abstract: Provided is a method of manufacturing a semiconductor device including a high-k dielectric thin layer formed using an interfacial reaction. The method includes the steps of: forming an oxide layer on a silicon substrate; depositing a metal layer on the oxide layer to form a metal silicate layer using an interfacial reaction between the oxide layer and the metal layer; forming a metal gate by etching the metal silicate layer and the metal layer; and forming a lightly doped drain (LDD) region and source and drain regions in the silicon substrate after forming the metal gate. In this method, a semiconductor device having high quality and performance can be manufactured by a simpler process at lower cost.

Abstract: A method of post-programming a flash memory device includes the steps of: post-programming memory cells of a selected word line in a predetermined unit; determining, after incrementing an address for selecting the next word line, whether the incremented address matches one of reference addresses; and varying the post-programming unit of the selected memory cells whenever the incremented address matches one of reference addresses.

Abstract: Provided is a method of fabricating a semiconductor device, the method including: forming an insulating layer on a single crystal substrate; etching the insulating layer in a predetermined pattern to expose the surface of the single crystal substrate; depositing an amorphous material on the insulating layer and the exposed surface of the single crystal substrate; and completely melting the amorphous material on the single crystal substrate and the insulating layer using laser annealing and crystallizing the melted amorphous material. The semiconductor device has a single crystalline silicon gate on the insulating layer.

Abstract: In a method for fabricating a semiconductor memory device and a semiconductor memory device fabricated by the method, the method includes forming a multi-layered dielectric structure including a first dielectric layer with an ion implantation layer and a second dielectric layer without an ion implantation layer, over a semiconductor substrate; forming nanocrystals in the first and second dielectric layers by diffusing ions of the ion implantation layer by thermally treating the multi-layered dielectric structure; and forming a gate electrode on the multi-layered dielectric structure.

Abstract: A system for remote controlling and monitoring a home appliance includes a first home appliance having a master function, at least one second home appliance having a slave function, and a communication line path for communication only between the first home appliance and at least one of the second home appliances. The master function is configured to control the slave function.

Abstract: The present invention relates to a process for preparing polyketone with improved catalytic activity and intrinsic viscosity, and specifically a process for preparing polyketone, using a mixed solvent of 40 to 60 mol % acetic acid and 40 to 60 mol % water, as a liquid medium, and the precursor of palladium chloride-1,3-bis[di(methoxyphenyl)phosphino]propane, as a catalyst component.

Abstract: Disclosed herein are a method and divider for dividing power between and supplying the parts of the power to respective radiation elements of an array antenna, and an antenna device using the divider. The division method includes the steps of dividing power, applied to a feeding unit, into two parts at a first stage of division, and supplying a first of the two parts to at least one central radiation element, and dividing a second of the two parts and supplying sub-parts of the second part to respective peripheral radiation elements, thereby supplying relatively high power to the central radiation element and relatively low power to the peripheral radiation elements.

Abstract: The present invention provides a fan apparatus which can reduce noise and enhance fan efficiency by employing a BLDC motor that can make stable drive of the fan and increase an air flow rate, and an outdoor unit of a front suction/discharge type in an air conditioner that can enhance heat exchange efficiency by employing the same.

Abstract: Provided is a Schottky barrier nanowire field effect transistor, which has source/drain electrodes formed of metal silicide and a channel formed of a nanowire, and a method for fabricating the same. The Schottky barrier nanowire field effect transistor includes: a channel suspended over a substrate and including a nanowire; metal silicide source/drain electrodes electrically connected to both ends of the channel over the substrate; a gate electrode disposed to surround the channel; and a gate insulation layer disposed between the channel and the gate electrode.

Abstract: Provided is a method for fabricating a Schottky barrier tunnel transistor (SBTT) that can fundamentally prevent the generation of a gate leakage current caused by damage of spacers formed on both sidewalls of a gate electrode. The method for fabricating a Schottky barrier tunnel transistor, which includes: a) forming a silicon pattern and a sacrificial pattern on a buried oxide layer supported by a support substrate; b) forming a source/drain region on the buried oxide layer exposed on both sides of the silicon pattern, the source/drain region being formed of a metal layer and being in contact with both sidewalls of the silicon pattern; c) removing the sacrificial pattern to expose the top surface of the silicon pattern; and d) forming a gate insulating layer and a gate electrode on the exposed silicon pattern.

Abstract: Fan apparatus including a fan, a shaft coupled to the fan for transmission of driving force from a motor to the fan, a rotor bushing of an insulating material joined to a rear end portion of the shaft, a rotor joined to the rotor bushing for transmission of the driving force to the shaft through the rotor bushing, and a stator mounted so as to be positioned on an inside of the rotor to form a BLDC motor together with the rotor, thereby reducing noise and enhancing fan efficiency by employing the BLDG motor which can make stable operation of the fan and increase an air flow rate.