Patents by Inventor Jong-Geon Lee
Jong-Geon Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11977780Abstract: A method for operating a Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) for DIMM-to-DIMM communication is provided. The NMP DIMM includes one or more ports for communicative connection to other NMP DIMMs. The method includes parsing, by one NMP DIMM, a NMP command received from a processor of a host platform, identifying data dependencies on one or more other NMP DIMMs based on the parsing, establishing communication with the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, receiving data from the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, processing the NMP command using the data received from one of the one or more other NMP DIMMs and data present in the one NMP DIMM, and sending a NMP command completion notification to the processor of the host platform.Type: GrantFiled: May 17, 2022Date of Patent: May 7, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eldho Mathew Pathiyakkara Thombra, Prashant Vishwanath Mahendrakar, Jin In So, Jong-Geon Lee
-
Patent number: 11922068Abstract: A Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) is provided that includes random access memory (RAM), a Near-Memory-Processing (NMP) circuit and a first control port. The NMP circuit is for receiving a command from a host system, determining an operation to be performed on the RAM in response to the command, and a location of data within the RAM with respect to the determined operation. The first control port interacts with a second control port of the host system to enable the NMP circuit to exchange control information with the host system in response to the received command.Type: GrantFiled: February 7, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eldho Mathew Pathiyakkara Thombra, Ravi Shankar Venkata Jonnalagadda, Prashant Vishwanath Mahendrakar, Jinin So, Jong-Geon Lee, Vishnu Charan Thummala
-
Publication number: 20240025377Abstract: An actuator for supplying compressed air for cleaning and drying a sensor of a vehicle, includes a compression unit configured to compress air from outside to form high-pressure compressed air, a drying unit configured to receive the compressed air compressed to a high pressure by the compression unit via a movement passage to remove moisture from the compressed air, and a storage tank connected to the drying unit via a connecting passage and configured to store the compressed air passing through the drying unit to be supplied to the vehicle, wherein the compressed air is stored in the storage tank so that high-pressure compressed air is generated and sprayed to the sensor of the vehicle, cleaning and drying the same in a short time.Type: ApplicationFiled: May 30, 2023Publication date: January 25, 2024Applicants: Hyundai Motor Company, Kia Corporation, DAEDONG MOVEL SYSTEM Co., Ltd.Inventors: Je Yeon Kim, Jong Geon Lee, Yoon Geun Cho, Byoung Jo Kim, Wan Cheol Lee, Yun Soo Kim
-
Patent number: 11797440Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.Type: GrantFiled: June 30, 2022Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Raghu Vamsi Krishna Talanki, Eldho Pathiyakkara Thombra Mathew, Vishnu Charan Thummala, Vinod Kumar Srinivasan, Jin In So, Jong-Geon Lee
-
Publication number: 20230302878Abstract: An air supply system for a vehicle includes a first system including a first compressor compressing ambient air, a heat exchanger connected to the first compressor to allow compressed air to flow therethrough, and a first condenser connected to the heat exchanger. The air supply system further includes a second system including a second compressor compressing a refrigerant, a second condenser disposed at a rear end of the second compressor, an expansion valve disposed at a rear end of the second compressor, and an evaporator disposed at a rear end of the expansion valve. The second compressor, the second condenser, the expansion valve, and the evaporator of the second system are sequentially connected by a refrigerant flow line, and a refrigerant pipe disposed in the evaporator of the second system and connected to the refrigerant flow line is connected to a refrigerant pipe for a first condenser.Type: ApplicationFiled: October 26, 2022Publication date: September 28, 2023Inventor: Jong Geon Lee
-
Publication number: 20230303036Abstract: A sensor cleaning apparatus includes an air compressor for compressing air, a compressor distributor connected to the air compressor, a nozzle connected to the compressor distributor for providing air to a sensor, and a control unit connected to at least one of the air compressor or the compressor distributor. The air compressor includes a housing that forms an internal space in which air may be compressed, and a cooling member provided on an external surface of the housing and connected to the compressor distributor.Type: ApplicationFiled: October 21, 2022Publication date: September 28, 2023Inventor: Jong Geon Lee
-
Publication number: 20230185487Abstract: A Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) is provided that includes random access memory (RAM), a Near-Memory-Processing (NMP) circuit and a first control port. The NMP circuit is for receiving a command from a host system, determining an operation to be performed on the RAM in response to the command, and a location of data within the RAM with respect to the determined operation. The first control port interacts with a second control port of the host system to enable the NMP circuit to exchange control information with the host system in response to the received command.Type: ApplicationFiled: February 7, 2022Publication date: June 15, 2023Inventors: ELDHO MATHEW PATHIYAKKARA THOMBRA, RAVI SHANKAR VENKATA JONNALAGADDA, PRASHANT VISHWANATH MAHENDRAKAR, JININ SO, JONG-GEON LEE, VISHNU CHARAN THUMMALA
-
Publication number: 20230046552Abstract: A Near Memory Processing (NMP) module including: a plurality of memory units: an Input/Output (I/O) interface configured to receive commands from a host system, wherein the host system includes a host memory controller configured to access the plurality of memory units: a decoder configured to decode the commands and generate a trigger; and an NMP memory controller configured to: receive the trigger from the decoder; and generate a signal in response to the trigger to synchronize the NMP module with the host system.Type: ApplicationFiled: July 27, 2022Publication date: February 16, 2023Inventors: Eldho Pathiyakkara Thombra Mathew, Prashant Vishwanath Mahendrakar, Jin In SO, Jong-Geon LEE
-
Publication number: 20230012707Abstract: A method and system for exchanging network packets in a memory system is provided. A size of each network packet to be transmitted is determined. Each network packets is segregated into one of plural queues based on the size of the network packet. Each network packet is transmitted over a shared memory, according to the queue in which the network packet is segregated.Type: ApplicationFiled: July 12, 2022Publication date: January 19, 2023Applicant: SAMSUNG ELECTRONICS CO, LTD.Inventors: Nitesh SHETTY, Rahul T R, Jin In SO, Jong- Geon LEE, Ravi Shankar Venkata JONNALAGADDA
-
Publication number: 20230004489Abstract: A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.Type: ApplicationFiled: June 30, 2022Publication date: January 5, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Raghu Vamsi Krishna TALANKI, Eldho Pathiyakkara Thombra Mathew, Vishnu Charan Thummala, Vinod Kumar Srinivasan, Jin ln So, Jong-Geon Lee
-
Patent number: 11531618Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.Type: GrantFiled: January 25, 2021Date of Patent: December 20, 2022Inventors: Kyungsoo Kim, Jinin So, Jong-Geon Lee, Yongsuk Kwon, Jin Jung, Jeonghyeon Cho
-
Publication number: 20220365726Abstract: A method for operating a Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) for DIMM-to-DIMM communication is provided. The NMP DIMM includes one or more ports for communicative connection to other NMP DIMMs. The method includes parsing, by one NMP DIMM, a NMP command received from a processor of a host platform, identifying data dependencies on one or more other NMP DIMMs based on the parsing, establishing communication with the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, receiving data from the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, processing the NMP command using the data received from one of the one or more other NMP DIMMs and data present in the one NMP DIMM, and sending a NMP command completion notification to the processor of the host platform.Type: ApplicationFiled: May 17, 2022Publication date: November 17, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eldho Mathew PATHIYAKKARA THOMBRA, Prashant Vishwanath MAHENDRAKAR, Jin In SO, Jong-Geon LEE
-
Publication number: 20210390049Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.Type: ApplicationFiled: January 25, 2021Publication date: December 16, 2021Inventors: Kyungsoo Kim, Jinin So, Jong-Geon Lee, Yongsuk Kwon, Jin Jung, Jeonghyeon Cho
-
Patent number: 10916274Abstract: A power management integrated circuit includes first pads, second pads, a third pad, and a fourth pad that are configured to be connected with an external device, a regulation block that receives first voltages from the first pads, converts the first voltages to second voltages, and outputs the second voltages to the second pads, a communication block that receives a command through the third pad and outputs an internal information request received together with the command responsive to the command, and a logic block that controls an operation of the regulation block, receives the internal information request from the communication block, and outputs internal state information to the fourth pad based on the internal information request.Type: GrantFiled: December 31, 2019Date of Patent: February 9, 2021Inventors: Jong-Geon Lee, Kyudong Lee, Jinseong Yun
-
Publication number: 20200335141Abstract: A power management integrated circuit includes first pads, second pads, a third pad, and a fourth pad that are configured to be connected with an external device, a regulation block that receives first voltages from the first pads, converts the first voltages to second voltages, and outputs the second voltages to the second pads, a communication block that receives a command through the third pad and outputs an internal information request received together with the command responsive to the command, and a logic block that controls an operation of the regulation block, receives the internal information request from the communication block, and outputs internal state information to the fourth pad based on the internal information request.Type: ApplicationFiled: December 31, 2019Publication date: October 22, 2020Inventors: Jong-Geon Lee, KYUDONG LEE, JINSEONG YUN
-
Patent number: 9803931Abstract: The handpiece includes; an outer housing of a bar shape; a cylindrical core inserted into the outer housing and having an air hole and a water hole; pipes respective inserted into the air hole and the water hole of the core; a rotor made with a cylindrical magnetic material and inserted into the core; cylindrical support rings forcedly fit to both sides of transfer shafts of the rotor; a pair of bearings respectively disposed at the front side and the rear side of the support rings; a coupling disposed in front of the rotor; a front housing joined to the front of the outer housing; a front cap disposed at the rear of the core; a rear cap disposed at the rear of the front cap and having a power supply terminal disposed at one side thereof; and a rear housing joined to the rear of the outer housing.Type: GrantFiled: December 5, 2012Date of Patent: October 31, 2017Assignee: MICRO-NX CO., LTDInventor: Jong Geon Lee
-
Publication number: 20140338872Abstract: The handpiece includes; an outer housing of a bar shape; a cylindrical core inserted into the outer housing and having an air hole and a water hole; pipes respective inserted into the air hole and the water hole of the core; a rotor made with a cylindrical magnetic material and inserted into the core; cylindrical support rings forcedly fit to both sides of transfer shafts of the rotor; a pair of bearings respectively disposed at the front side and the rear side of the support rings; a coupling disposed in front of the rotor; a front housing joined to the front of the outer housing; a front cap disposed at the rear of the core; a rear cap disposed at the rear of the front cap and having a power supply terminal disposed at one side thereof; and a rear housing joined to the rear of the outer housing.Type: ApplicationFiled: December 5, 2012Publication date: November 20, 2014Inventor: Jong Geon Lee
-
Patent number: 7519873Abstract: Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.Type: GrantFiled: September 8, 2006Date of Patent: April 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Man Shin, Seung-Jin Seo, You-Keun Han, Hui-Chong Shin, Jong-Geon Lee, Kyung-Hee Han
-
Publication number: 20070030814Abstract: A memory module and method thereof are provided. In the example method, a test signal may be applied to a plurality of memory chips included in the memory module. Output data from the plurality of memory chips may be received in response to the applied test signal. The received, output data may be divided into a plurality of groups. At least one of the plurality of groups may be selected in response to an output group selection signal. The at least one selected group may be output (e.g., to an external device). The example memory module may include a plurality of chips and a hub. The example memory module may be configured to perform the above-described example method.Type: ApplicationFiled: July 20, 2006Publication date: February 8, 2007Inventors: Seung-Man Shin, Hui-Chong Shin, Jong-Geon Lee, Kyung-Hee Han
-
Publication number: 20070022335Abstract: Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.Type: ApplicationFiled: September 8, 2006Publication date: January 25, 2007Inventors: Seung-Man Shin, Seung-Jin Seo, You-Keun Han, Hui-Chong Shin, Jong-Geon Lee, Kyung-Hee Han