Abstract: There is provided a method of forming a film of a semiconductor device. The method includes a step of adsorbing a liquefied metal ion source on the substrate; rinsing the substrate to remove any liquefied metal ion source that is not adsorbed to the substrate; depositing a metal layer on the substrate by reducing the liquefied metal ion source that is adsorbed on the substrate with a liquefied reducing agent; and rinsing the substrate to remove the remaining liquefied reducing agent and any reaction residual.

Abstract: A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semiconductor plug may be formed in the contact hole and on portions of the interlayer insulating layer adjacent the contact hole opposite the semiconductor substrate, and portions of the interlayer insulating layer opposite the semiconductor substrate may be free of the single crystal semiconductor plug. Portions of the single crystal semiconductor plug in the contact hole may be removed while maintaining portions of the single crystal semiconductor plug on portions of the interlayer insulating layer adjacent the contact hole as a single crystal semiconductor contact pattern.

Abstract: There is provided a method of forming a semiconductor device having stacked transistors. When forming a contact hole for connecting the stacked transistors to each other, ohmic layers on the bottom and the sidewall of the common contact hole are separately formed. As a result, the respective ohmic layers are optimally formed to meet requirements or conditions. Accordingly, the contact resistance of the common contact may be minimized so that it is possible to enhance the speed of the semiconductor device.

Abstract: A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.

Abstract: Methods of forming field effect transistors according to embodiments of the invention include forming a conductive gate electrode (e.g., polysilicon gate electrode) on a semiconductor substrate and forming a first metal layer on the conductive gate electrode. This first metal layer may include a material selected from a group consisting of nickel, cobalt, titanium, tantalum and tungsten. The first metal layer and the conductive gate electrode are thermally treated for a sufficient duration to convert a first portion of the conductive gate electrode into a first metal silicide region. The first metal layer and the first metal silicide region are then removed to expose a second portion of the conductive gate electrode. A second metal layer is then formed on the second portion of the conductive gate electrode. This second metal layer may include a material selected from a group consisting of nickel, cobalt, titanium, tantalum and tungsten.

Abstract: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.

Abstract: A stacked semiconductor device comprises a lower transistor formed on a semiconductor substrate, a lower interlevel insulation film formed on the semiconductor substrate over the lower transistor, an upper transistor formed on the lower interlayer insulation film over the lower transistor, and an upper interlevel insulation film formed on the lower interlevel insulation film over the upper transistor. The stacked semiconductor device further comprises a contact plug connected between a drain or source region of the lower transistor and a source or drain region of the upper transistor, and an extension layer connected to a lateral face of the source or drain region of the upper transistor to enlarge an area of contact between the source or drain region of the upper transistor and a side of the contact plug.

Abstract: A method of forming an ohmic contact layer including forming an insulation layer pattern on a substrate, the insulation pattern layer having an opening selectively exposing a silicon bearing layer, forming a metal layer on the exposed silicon bearing layer using an electrode-less plating process, and forming a metal silicide layer from the silicon bearing layer and the metal layer using a silicidation process. Also, a method of forming metal wiring in a semiconductor device using the foregoing method of forming an ohmic contact layer.

Abstract: Provided are methods of manufacturing a semiconductor device. Some embodiments of such methods may include forming a preliminary gate pattern on a substrate. The preliminary gate pattern may include silicon. Methods may include forming an insulation layer pattern on the substrate after forming the preliminary gate pattern. The insulation layer pattern exposes an upper face of the preliminary gate pattern. Methods may include forming a metal layer on the upper face of the preliminary gate pattern via an electroless plating process. Methods may include forming a gate pattern including a metal silicide from a reaction between the preliminary gate pattern and the metal layer by performing a heat treatment process.

Abstract: A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.

Abstract: A method of forming a cobalt disilicide layer and a method of manufacturing a semiconductor device using the same are provided. The method of forming a cobalt disilicide layer includes forming a cobalt layer on at least a silicon surface of a semiconductor device using metal organic chemical vapor deposition by supplying a cobalt precursor having a formula Co2(CO)6(R1—C?C—R2), where R1 is H or CH3, and R2 is hydrogen, t-butyl, phenyl, methyl, or ethyl, as a source gas. Then, a capping layer is formed on the cobalt layer. A first thermal treatment is then performed on the semiconductor device in an ultra high vacuum, for example, under a pressure of 10?9-10?3 torr, to react silicon with cobalt. Cobalt unreacted during the first thermal treatment and the capping layer are then removed and a second thermal treatment is performed on the semiconductor device to form the cobalt disilicide (CoSi2) layer.

Abstract: In an embodiment a first silicon pattern and a second silicon pattern are formed on a substrate. The second silicon pattern has a lower top surface than the first silicon pattern. A first spacer covering a sidewall of the first silicon pattern is formed and a second spacer covering a sidewall of the second silicon pattern is formed. A silicide process is performed to silicidize the first silicon pattern and the second silicon pattern. Work functions of the first and second silicon patterns can be controlled and optimized by controlling the composition of the first and second silicon patterns.

Abstract: A semiconductor device is fabricated by forming a gate electrode structure, comprising a gate oxide layer pattern, a polysilicon layer pattern, and sidewall spacers on a silicon substrate, forming source/drain regions on both sides of the gate electrode structure in the silicon substrate, depositing a physical vapor deposition (PVD) cobalt layer on the gate electrode structure using PVD, depositing a chemical vapor deposition (CVD) cobalt layer on the PVD cobalt layer using CVD, annealing the silicon substrate to react the PVD and CVD cobalt layers with polysilicon on an upper surface of the gate electrode structure, stripping at least a portion of the PVD cobalt layer and the CVD cobalt layer that has not reacted, and annealing the silicon substrate after stripping the at least the portion of the PVD cobalt layer and the CVD cobalt layer.

Abstract: A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconductor device is annealed to react the double metal layer with the silicon surface. At least a portion of the double layer that has not reacted with the silicon surface is stripped. The semiconductor device is annealed after stripping at least the portion of the double metal layer.

Abstract: A method of forming a silicide film can include forming a first metal film on a silicon substrate and forming a second metal film on the first metal film at a temperature sufficient to react a first portion of the first metal film in contact with the silicon substrate to form a metal-silicide film. The second metal film and a second portion of the first metal film can be removed so that a thin metal-silicide film remains on the silicon substrate. Then, a metal wiring film can be formed on the thin metal-silicide film and the metal wiring film can be etched.

Abstract: The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C?C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.

Abstract: A method of forming a composite metal silicide layer is disclosed in which a PVD-metal layer is deposited on a silicon layer using a Physical Vapor Deposition (PVD) process, and is substantially simultaneously silicidated to form a PVD-metal silicide layer. Un-reacted portions of the PVD-metal layer are then removed and a CVD-metal layer is formed on the PVD-metal silicide layer using a Chemical Vapor Deposition (CVD) process. A first heat treatment is performed to silicidate a portion of the CVD-metal layer contacting the PVD-metal silicide layer and thereby form a composite metal silicide layer. Un-reacted residual portions of the CVD-metal layer are removed and a second heat treatment is performed on the composite metal silicide layer at a higher temperature than the first heat treatment.

Abstract: The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C?C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.

Abstract: A gate is silicided through its sides while limiting silicidation through the top of the gate. A blocking layer may be formed over the gate layer, and the sidewalls of the gate layer are exposed. A layer of metal is formed on the sidewalls of the gate and thermally treated to silicide the gate layer. The sidewalls of the gate maybe exposed through an etching process in which a silicide layer formed over the blocking layer is used as an etch mask.

Abstract: Methods of forming a metal salicide layer can include forming a metal layer on a substrate and forming a metal silicide layer on the metal layer using a first thermal process at a first temperature. Then a second process is performed, in-situ with the first thermal process, on the metal layer at a second temperature that is less than the first temperature.