Abstract: A refrigerator includes a rotating bar configured to seal a gap between one pair of doors. The rotating bar includes a case provided with an accommodating space therein while having one surface thereof open, a heat insulation member accommodated in the accommodating space, a cover configured to cover the one surface of the case that is open, and a metallic plate being coupled to an outer side of the cover. The cover includes a heat conduction blocking part being protruded to both sides of the metallic plate while having a bent-shape cross section so as to prevent heat from being transmitted to both side surfaces of the rotating bar after being heat conducted along the metallic plate.

Abstract: A refrigerator provided with a rotating bar configured to seal a gap between one pair of doors, capable of preventing the door from being incompletely closed due to an erroneous operation of the rotating bar, the rotating bar capable of sealing a gap formed between the rotating bar and a body as well as a gap formed between one pair of doors, the rotating bar being elastically supported by an elastic member so as to move by receiving an external force from a guide part provided on the body, the rotating bar including a sealing member protruding from the rotating bar so as to seal a gap between the rotating bar and the body.

Abstract: A refrigerator provided with a door having the height thereof easily adjustable, the refrigerator including a hinge bracket configured to connect a body to a door of the refrigerator, a hinge shaft coupled to the hinge bracket so as to enable ascending and descending, and a door support on which a lower surface of the door is placed, wherein the hinge shaft includes a shaft adjusting part formed at an upper side of the hinge bracket to easily rotate the hinge shift. A user allows the hinge shaft and the door support by rotating the shaft adjusting part, thereby adjusting the door supported by the door support.

Abstract: The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

Abstract: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.

Abstract: A refrigerator including support ribs provided on both side walls of storage chambers so as to support both sides of shelves, each of which includes a tempered glass panel on which food is placed, and stopper members provided at both sides of the lower surface of the tempered glass panel, each support rib including a front rib, a rear rib, and a latch groove provided between the front rib and the rear rib such that each stopper member is inserted into the latch groove, and inclination prevention ribs, each of which is provided above the rear rib and supports the upper surface of each shelf, thereby improving assembly efficiency and productivity.

Abstract: A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.

Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.

Abstract: The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

Abstract: Embodiments of the invention generally provide a method and apparatus for transmitting and receiving clock signals. In one embodiment, the method includes receiving, at a memory device, a first clock signal and a second clock signal. The frequency of the first clock signal may be less than the frequency of the second clock signal. The method further includes performing two or more data access operations using the second clock signal. One of the two or more data access operations may include a read operation and one of the two or more data access operations may include a write operation. The method also includes performing a command processing operation using the first clock signal.

Abstract: Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.

Abstract: Embodiments of the invention generally provide a method and apparatus for correcting errors in a memory device. In one embodiment, the method includes receiving a read command and a read address for the read command and reading data from a first location of the memory device corresponding to the read address. The method also includes reading error correction information corresponding to the read address. If the error correction information indicates an error in the data, the error in the data is corrected to produce corrected data and the corrected data is output from the memory device. The corrected data is also written back to a second location in the memory device corresponding to the read address.

Abstract: The present invention relates to computing circuits and method for running an MPEG-2 AAC or MPEG-4 AAC algorithm efficiently, which is used as an audio compression algorithm in multi-channel high-quality audio systems, on programmable processors. In accordance with the present invention, the IMDCT process which takes large part of the amount of the operations in implementation of an MPEG-2/4 AAC algorithm can be performed in efficient. In addition, while the architecture of the existing digital signal processor is still used, the performance can be improved by means of the addition of the architecture of the address generator, Huffman decoder, and bit processing architecture. After all, to design and change the programmable processor is facilitated.

Abstract: Methods and apparatus that provide an additional level(s) of hierarchy within a bank of a Dynamic Random Access Memory (DRAM) are provided. The bank has a plurality of separately addressable sub-banks.

Abstract: A computing system having a plurality of processors including a first processor configured with an address port and a second processor configured with an address port, and a memory device having a first port configured as an address port and to alternatively interface with the address port of the first processor and the address port of the second processor.

Abstract: A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits. Both the DLL circuit and voltage generator draw current, which is multiplied by the number of memory components in a memory system. By operating a single DLL circuit and/or voltage generator in or associated with the memory interface, that generates a read clock signal and/or various voltage levels, respectively, for all memory components in the memory system, power consumption may be significantly reduced.

Abstract: Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.