Patents by Inventor Jong-Hoon Oh

Jong-Hoon Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self-diagnostic scheme for detecting errors
    Patent number: 7694196
    Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: April 6, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Josef Schnell, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins
  • Structure to share internally generated voltages between chips in MCP
    Patent number: 7688665
    Abstract: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: March 30, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Jung Pill Kim, Jong Hoon Oh, Oliver Kiehl, Josef Schnell, Klaus Hummler, Wayne Frederick Ellis, Octavian Beldiman, Lee Ward Collins
  • Multichip package with clock frequency adjustment
    Patent number: 7617067
    Abstract: One embodiment of the present invention provides a multi-chip package including a logic device providing a clock signal having a frequency and a memory device. The memory device receives the clock signal and operates at the clock signal frequency. The memory device includes a temperature sensor providing a temperature signal indicative of a temperature of the memory device, wherein the logic device adjusts the clock signal frequency bases on the temperature signal.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: November 10, 2009
    Assignee: Infineon Technologies AG
    Inventor: Jong-Hoon Oh
  • Abbreviated burst data transfers for semiconductor memory
    Patent number: 7617354
    Abstract: An integrated circuit having a nominal minimum burst length defined by a nominal data prefetch size transfers data by accepting an abbreviated burst data read request directed to a first bank, prefetching less than the nominal data prefetch size, and providing the data in an abbreviated burst data transfer less than the nominal minimum burst length.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: November 10, 2009
    Assignee: Qimonda North America Corp.
    Inventor: Jong-Hoon Oh
  • Technique to read special mode register
    Patent number: 7610455
    Abstract: Embodiments are provided in which a method and apparatus for accessing a special mode register of a memory device are described. A command to access the special mode register is detected. The command is executed by driving data from the special mode register onto a data bus. The command self-terminates by placing the data bus in a high impedance state. One or more unused address bits may specify one of a plurality of special mode registers to be accessed by the command. The command to access the special mode register may be incapable of changing one or more bits in a mode register.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: October 27, 2009
    Assignee: Infineon Technologies AG
    Inventor: Jong-Hoon Oh
  • METHOD FOR STACKING CHIPS IN A MULTI-CHIP PACKAGE
    Publication number: 20090200652
    Abstract: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 13, 2009
    Inventors: Jong Hoon Oh, Klaus Hummler, Oliver Kiehl, Josef Schnell, Wayne Frederick Ellis, Jung Pil Kim, Lee Ward Collins, Octavian Beldiman
  • SEMICONDUCTOR MEMORY HAVING A BANK WITH SUB-BANKS
    Publication number: 20090196116
    Abstract: Methods and apparatus that provide an additional level(s) of hierarchy within a bank of a Dynamic Random Access Memory (DRAM) are provided. The bank has a plurality of separately addressable sub-banks.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 6, 2009
    Inventor: JONG-HOON OH
  • Memory configured on a common substrate
    Patent number: 7539034
    Abstract: A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: May 26, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jung Pill Kim, Jong-Hoon Oh, Oliver Kiehl, Josef Schnell, Klaus Hummler, Wayne Ellis, Octavian Beldiman, Lee Collins
  • SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS
    Publication number: 20090129186
    Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 21, 2009
    Inventors: Josef Schnell, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins
  • METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH MASTER-SLAVE ARCHITECTURE
    Publication number: 20090113158
    Abstract: Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Inventors: Josef Schnell, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins
  • METHOD AND APPARATUS FOR IMPLEMENTING MEMORY ENABLED SYSTEMS USING MASTER-SLAVE ARCHITECTURE
    Publication number: 20090113078
    Abstract: Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Inventors: JOSEF SCHNELL, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins
  • STRUCTURE TO SHARE INTERNALLY GENERATED VOLTAGES BETWEEN CHIPS IN MCP
    Publication number: 20090080279
    Abstract: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Inventors: JUNG PILL KIM, Jong Hoon Oh, Oliver Kiehl, Josef Schnell, Klaus Hummler, Wayne Frederick Ellis, Octavian Beldiman, Lee Ward Collins
  • METHOD AND STRUCTURE OF EXPANDING, UPGRADING, OR FIXING MULTI-CHIP PACKAGE
    Publication number: 20090079055
    Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Inventors: JONG HOON OH, Klaus Hummler, Oliver Kiehl, Josef Schnell, Wayne Frederick Ellis, Jung Pill Kim, Lee Ward Collins, Octavian Beldiman
  • Digital amplifier, pulse width modulator thereof and method for reducing pop noise for the same
    Patent number: 7508873
    Abstract: A pulse width modulator for use in a digital amplifier, includes a pop noise reducer for reducing pop noise by controlling a width and a phase of a pulse of a PWM signal output from the pulse width modulator, wherein the pop noise reducer contains: a PWM pulse register for storing a width and a phase values of a pulse of the PWM signal; and a pulse generator for outputting the PWM signal according to the values stored in the PWM pulse register. The pulse width modulator reduces pop noise generated when power supply to a digital amplifier is started and interrupted.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: March 24, 2009
    Assignee: Pulsus Technologies
    Inventors: Tae Ho Kim, Jong Hoon Oh
  • INTEGRATED CIRCUIT INCLUDING MULTIPLE MEMORY DEVICES
    Publication number: 20090031077
    Abstract: An integrated circuit includes a data bus and a first memory device coupled to the data bus. The first memory device is configured to provide a first signal in response to completing a power-up sequence of the first memory device. The integrated circuit includes a second memory device coupled to the data bus. The second memory device is configured to provide a second signal in response to completing a power-up sequence of the second memory device. The integrated circuit includes a controller configured to access the first memory device and the second memory device based on the first signal and the second signal.
    Type: Application
    Filed: July 23, 2007
    Publication date: January 29, 2009
    Inventors: Ralf Klein, Jong Hoon Oh
  • Early Write Method and Apparatus
    Publication number: 20090021995
    Abstract: A write operation is performed in a memory device. During a first stage of the write operation, a signal is applied to gating circuitry at a first voltage level for coupling a data bus line to a bit line when the data bus line is unmasked and for decoupling the data bus line from the bit line when the data bus line is masked. During one or more subsequent stages of the write operation, the signal voltage level is changed for enabling completion of the write operation.
    Type: Application
    Filed: July 19, 2007
    Publication date: January 22, 2009
    Inventor: Jong-Hoon Oh
  • MEMORY REFRESH SYSTEM AND METHOD
    Publication number: 20080313494
    Abstract: A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.
    Type: Application
    Filed: June 15, 2007
    Publication date: December 18, 2008
    Applicant: QIMONDA NORTH AMERICA CORP.
    Inventors: Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Josef Schnell, Octavian Beldiman, Lee Ward Collins
  • Mobile phone
    Patent number: D584264
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: January 6, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Hoon Oh, Young Ju Yeo, Chang Hwan Hwang
  • Portable phone
    Patent number: D586311
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: February 10, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Oh, Young-Ju Yeo
  • Mobile phone
    Patent number: D615955
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: May 18, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Hoon Oh, Young-Keun Lee