Abstract: A method of manufacturing a display device in a chamber in which a material including yttrium is coated on an inner surface includes: forming a first layer pattern by dry etching on a substrate; depositing a second layer material on the first layer pattern; forming a photoresist pattern on the second layer material; completing a second layer pattern by using the photoresist pattern as an etch mask; and performing an additional acid etching process by using an etching solution including at least one of hydrochloric acid, sulfuric acid, or nitric acid before the forming of the photoresist pattern on the second layer material after the dry etching to form the first layer pattern.

Abstract: A method of fabricating a conductive pattern includes forming a conductive metal material layer and a conductive capping material layer on a substrate, forming a photoresist pattern as an etching mask on the conductive capping material layer, forming a first conductive capping pattern by etching the conductive capping material layer with a first etchant, forming a conductive metal layer and a second conductive capping pattern by etching the conductive metal material layer and the first conductive capping pattern with a second etchant, and forming a conductive capping layer by etching the second conductive capping pattern with a third etchant. The second conductive capping pattern includes a first region overlapping the conductive metal layer and a second region not overlapping the conductive metal layer, and the forming of the conductive capping layer includes etching the second region of the second conductive capping pattern to form the conductive capping layer.

Abstract: A transistor array substrate includes a substrate (having a first trench), a gate electrode (in the first trench), an insulating film, a gate line, a data line, a source electrode, and a drain electrode. The insulating film includes second, third, fourth, fifth, and sixth trenches. The gate line is in the second trench and is not parallel to the data line. The data line includes a first section and a second section that are separated by the gate line and respectively in the third and fourth trenches. The source electrode and the drain electrode are respectively in the fifth and sixth trenches. The source electrode is electrically connected to the data line. The gate electrode is electrically connected to the gate line.

Abstract: A transistor array substrate includes a substrate (having a first trench), a gate electrode (in the first trench), an insulating film, a gate line, a data line, a source electrode, and a drain electrode. The insulating film includes second, third, fourth, fifth, and sixth trenches. The gate line is in the second trench and is not parallel to the data line. The data line includes a first section and a second section that are separated by the gate line and respectively in the third and fourth trenches. The source electrode and the drain electrode are respectively in the fifth and sixth trenches. The source electrode is electrically connected to the data line. The gate electrode is electrically connected to the gate line.

Abstract: There is provided a display device. The display device includes a first substrate, a second substrate that faces the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. One of the first substrate and the second substrate includes a base substrate and a light blocking pattern disposed on a surface that faces the other surface of both surfaces of the base substrate, the light blocking pattern exposing a part of the base substrate. The light blocking pattern includes a semi-transmission reflective layer a disposed on the base substrate, a phase matching layer disposed on the semi-transmission reflective layer, and a reflective metal layer disposed on the phase matching layer. The phase matching layer and the reflective metal layer include materials having substantially the same etching rate.

Abstract: A method of forming a thin film pattern includes providing a thin film on a substrate, providing a photoresist on the thin film, forming a first photoresist pattern having a first packing density by exposing and developing the photoresist, etching the thin film by using the first photoresist pattern as a mask, processing the first photoresist pattern to convert the first photoresist pattern into a second photoresist pattern having a second packing density, which is lower than the first packing density, and stripping the second photoresist pattern by spraying steam onto the second photoresist pattern.

Abstract: A thin film transistor array substrate includes a first conductive pattern group including a gate line extending along a first direction, data lines extending along a second direction crossing the first direction and spaced apart from each other along the second direction with the gate line there between, and a gate electrode protruding from the gate line, an active pattern disposed on the gate electrode to overlap the gate electrode, a second conductive pattern group including a bridge pattern coupling the data lines, a source electrode extending to an upper portion of the active pattern from the bridge pattern and a drain electrode spaced apart from the source electrode, facing the source electrode and disposed on the active pattern and metal patterns each stacked between the active pattern and the source electrode and between the active pattern and the drain electrode.

Abstract: A method of forming a thin film pattern includes providing a thin film on a substrate, providing a photoresist on the thin film, forming a first photoresist pattern having a first packing density by exposing and developing the photoresist, etching the thin film by using the first photoresist pattern as a mask, processing the first photoresist pattern to convert the first photoresist pattern into a second photoresist pattern having a second packing density, which is lower than the first packing density, and stripping the second photoresist pattern by spraying steam onto the second photoresist pattern.

Abstract: A touch screen panel and manufacturing method thereof are disclosed. In one aspect, the touch screen panel includes a substrate having a touch area and a peripheral area that surrounds the touch area and a plurality of first touch electrode patterns that are formed in the touch area, extend in a first direction, and are configured to transmit a first touch signal. The touch panel also includes a plurality of second touch electrode patterns that are formed in the touch area, extend in a second direction crossing the first direction, and are configured to transmit a second touch signal and a plurality of first driving circuit wirings that are formed in the peripheral area and are respectively electrically connected to the first touch electrode patterns. The first driving circuit wirings include a low resistance wiring layer.

Abstract: There is provided a display device. The display device includes a first substrate, a second substrate that faces the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. One of the first substrate and the second substrate includes a base substrate and a light blocking pattern disposed on a surface that faces the other surface of both surfaces of the base substrate, the light blocking pattern exposing a part of the base substrate. The light blocking pattern includes a semi-transmission reflective layer a disposed on the base substrate, a phase matching layer disposed on the semi-transmission reflective layer, and a reflective metal layer disposed on the phase matching layer. The phase matching layer and the reflective metal layer include materials having substantially the same etching rate.

Abstract: An etchant composition is provided comprising a persulfate from 0.5 to 20 wt %; a fluoride compound from 0.01 to 2 wt %; an inorganic acid from 1 to 10 wt %; a N (nitrogen atom)-containing heterocyclic compound from 0.5 to 5 wt %; a chloride compound from 0.1 to 5 wt %; a copper salt from 0.05 to 3 wt %; an organic acid or an organic acid salt from 0.1 to 10 wt %; an electron-donating compound from at 0.1 to 5 wt %; and a solvent of the residual amount. Also provided is a method of manufacturing a display device by using the same.

Abstract: An array substrate for display devices is provided. According to an exemplary embodiment, the array substrate for display device includes: a plurality of gate lines that extend along a first direction; and a data line that is formed by connecting a plurality of first sub-data lines extending along a second direction and a plurality of second sub-data lines extending along a third direction, wherein the gate lines overlap the second sub-data lines with an insulating layer interposed therebetween.

Abstract: A thin film transistor array panel includes: a gate line on a substrate and including a gate electrode; a first gate insulating layer on the substrate and the gate line, the first gate insulting layer including a first portion adjacent to the gate line and a second portion overlapping the gate line and having a smaller thickness than that of the first portion; a second gate insulating layer on the first gate insulating layer; a semiconductor layer on the second gate insulating layer; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a passivation layer on the second gate insulating layer, the source electrode and the drain electrode; and a pixel electrode on the passivation layer and connected with the drain electrode. The first gate insulating layer and the second gate insulating layer have stress in opposite directions from each other.

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract: A thin film transistor array substrate includes a first conductive pattern group including a gate line extending along a first direction, data lines extending along a second direction crossing the first direction and spaced apart from each other along the second direction with the gate line there between, and a gate electrode protruding from the gate line, an active pattern disposed on the gate electrode to overlap the gate electrode, a second conductive pattern group including a bridge pattern coupling the data lines, a source electrode extending to an upper portion of the active pattern from the bridge pattern and a drain electrode spaced apart from the source electrode, facing the source electrode and disposed on the active pattern and metal patterns each stacked between the active pattern and the source electrode and between the active pattern and the drain electrode.

Abstract: A liquid crystal display includes a first substrate, a gate line which includes a gate electrode, a gate insulating layer, a semiconductor stripe layer which is separated from the gate line in a plan view, a semiconductor island, a data line, a source electrode and a drain electrode, an interlayer insulating layer in which a data line exposure hole which exposes a part of the data line is defined, a connecting member which is disposed on the interlayer insulating layer and is connected to the data lines which are disposed on and below the gate line through the data line exposure hole in plan view; and a pixel electrode which is disposed on the interlayer insulating layer and is separated from the connecting member, where the connecting member is directly connected to the source electrode and the pixel electrode is directly connected to the drain electrode.

Abstract: A thin film transistor array panel includes: a gate line on a substrate and including a gate electrode; a first gate insulating layer on the substrate and the gate line, the first gate insulting layer including a first portion adjacent to the gate line and a second portion overlapping the gate line and having a smaller thickness than that of the first portion; a second gate insulating layer on the first gate insulating layer; a semiconductor layer on the second gate insulating layer; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a passivation layer on the second gate insulating layer, the source electrode and the drain electrode; and a pixel electrode on the passivation layer and connected with the drain electrode. The first gate insulating layer and the second gate insulating layer have stress in opposite directions from each other.

Abstract: An array substrate for display devices is provided. According to an exemplary embodiment, the array substrate for display device includes: a plurality of gate lines that extend along a first direction; and a data line that is formed by connecting a plurality of first sub-data lines extending along a second direction and a plurality of second sub-data lines extending along a third direction, wherein the gate lines overlap the second sub-data lines with an insulating layer interposed therebetween.

Abstract: A liquid crystal display includes: a substrate; a gate line and a data line disposed on the substrate; a semiconductor layer disposed on the substrate; first and second field generating electrodes disposed on the substrate; and a first protecting layer formed from the same layer as the first field generating electrode and covering at least a portion of the data line.

Abstract: A etchant composition that includes, based on a total weight of the etchant composition, about 0.5 wt % to about 20 wt % of a persulfate, about 0.5 wt % to about 0.9 wt % of an ammonium fluoride, about 1 wt % to about 10 wt % of an inorganic acid, about 0.5 wt % to about 5 wt % of a cyclic amine compound, about 0.1 wt % to about 10.0 wt % of a sulfonic acid, about 5 wt % to about 10 wt % of an organic acid or a salt thereof, and a remainder of water. The etchant composition may be configured to etch a metal layer including copper and titanium, to form a metal wire that may be included in a thin film transistor array panel of a display device.