Patents by Inventor Jong-Kai Lin

Jong-Kai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8385084
    Abstract: A shielding structure is provided for shielding a signal path extending between a first layer and a second layer in an electronic device at a transition region with a transition that extends in a first direction and a second direction orthogonal to the first direction. The shielding structure includes a shielding structure portion, which includes a first shielding via in proximity to a first area of the signal path at the transition; a second shielding via in proximity to a second area of the signal path at the transition; and an area metallization electrically coupled to the first shielding via.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: February 26, 2013
    Inventors: Jinbang Tang, Jong-Kai Lin, Ronald V. McBean
  • Patent number: 8097494
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: January 17, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel Frear, Jong-Kai Lin, Marc A. Mangrum, Robert E. Booth, Lawrence N. Herr, Kenneth R. Burch
  • Patent number: 8004068
    Abstract: Embodiments include shielded multi-layer packages for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: August 23, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Jong-Kai Lin
  • Publication number: 20110075394
    Abstract: A shielding structure is provided for shielding a signal path extending between a first layer and a second layer in an electronic device at a transition region with a transition that extends in a first direction and a second direction orthogonal to the first direction. The shielding structure includes a shielding structure portion, which includes a first shielding via in proximity to a first area of the signal path at the transition; a second shielding via in proximity to a second area of the signal path at the transition; and an area metallization electrically coupled to the first shielding via.
    Type: Application
    Filed: December 8, 2010
    Publication date: March 31, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jinbang Tang, Jong-Kai Lin, Ronald V. McBean
  • Patent number: 7869225
    Abstract: A shielding structure is provided for shielding a signal path extending between a first layer and a second layer in an electronic device at a transition region with a transition that extends in a first direction and a second direction orthogonal to the first direction. The shielding structure includes a shielding structure portion, which includes a first shielding via in proximity to a first area of the signal path at the transition; a second shielding via in proximity to a second area of the signal path at the transition; and an area metallization electrically coupled to the first shielding via.
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: January 11, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Jong-Kai Lin, Ronald V. McBean
  • Publication number: 20110003435
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Application
    Filed: January 15, 2010
    Publication date: January 6, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: JINBANG TANG, DARREL FREAR, JONG-KAI LIN, MARC A. MANGRUM, ROBERT E. BOOTH, LAWRENCE N. HERR, KENNETH R. BURCH
  • Publication number: 20100044840
    Abstract: Embodiments include shielded multi-layer packages for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.
    Type: Application
    Filed: October 27, 2009
    Publication date: February 25, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jinbang Tang, Jong-Kai Lin
  • Patent number: 7651889
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel Frear, Jong-Kai Lin, Marc A. Mangrum, Robert E. Booth, Lawrence N. Herr, Kenneth R. Burch
  • Patent number: 7648858
    Abstract: Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: January 19, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Jong-Kai Lin
  • Publication number: 20090075428
    Abstract: Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.
    Type: Application
    Filed: December 20, 2007
    Publication date: March 19, 2009
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Jinbang Tang, Darrel Frear, Jong-Kai Lin, Marc A. Mangrum, Robert E. Booth, Lawrence N. Herr, Kenneth R. Burch
  • Publication number: 20090072357
    Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a plurality of modules (30-33) to a process carrier (10) using a double side adhesive tape (12) before encapsulating the modules with a molding compound (16), and then forming shielding via ring structures (51-54) in the molding compound (16) to surround and shield each module. After removing the adhesive tape (12) to expose a surface of the encapsulated modules, a multi-layer circuit substrate (101) is formed over the exposed surface, where the circuit substrate includes shielding via structures (121-124) that are aligned with and electrically connected to the shielding via ring structures (51-54), thereby encircling and shielding the circuit module(s).
    Type: Application
    Filed: September 13, 2007
    Publication date: March 19, 2009
    Inventors: Jinbang Tang, Darrel R. Frear, Jong-Kai Lin
  • Publication number: 20080315371
    Abstract: Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate (102) (e.g., chip carrier) has an adhesive layer (104), where electronic components (106, 108) are attached. An insulating layer (110) is formed over the plurality of electronic components, and a conductive encapsulant structure (115) is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry (140) is formed over, and in electrical communication with, the plurality of electronic components. A shielding via (150) is formed through the multilayer circuitry such that it contacts the conductive encapsulant.
    Type: Application
    Filed: June 19, 2007
    Publication date: December 25, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jinbang Tang, Jong-Kai Lin
  • Publication number: 20080315376
    Abstract: An electromagnetic interference (EMI) and/or electromagnetic radiation shield is formed on a plurality of encapsulated modules by attaching a molded package panel to a process carrier (10) using a double side adhesive tape (12) before singulating the individual modules without separating them from the double side adhesive tape. By forming a conductive layer (50) over a mold encapsulant (16) and on the sidewalls of grooves (40-47) that are cut through the mold encapsulant (16) and underlying circuit substrate (14), the conductive layer (50) may be electrically coupled to one or more conductive connection pads (61-66) by virtue of the placement of the conductive connection pads at the periphery or side of the circuit substrate (14).
    Type: Application
    Filed: June 19, 2007
    Publication date: December 25, 2008
    Inventors: Jinbang Tang, Jong-Kai Lin
  • Publication number: 20080266829
    Abstract: A shielding structure is provided for shielding a signal path extending between a first layer and a second layer in an electronic device at a transition region with a transition that extends in a first direction and a second direction orthogonal to the first direction. The shielding structure includes a shielding structure portion, which includes a first shielding via in proximity to a first area of the signal path at the transition; a second shielding via in proximity to a second area of the signal path at the transition; and an area metallization electrically coupled to the first shielding via.
    Type: Application
    Filed: April 30, 2007
    Publication date: October 30, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jinbang Tang, Jong-Kai Lin, Ronald V. McBean
  • Patent number: 6953985
    Abstract: An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements (340) sealed to a MEMS device die array (300) to produce a sealed MEMS device package array (330). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: October 11, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jong-Kai Lin, William H. Lytle, Owen Fay, Steven Markgraf, Henry G. Hughes, Craig Amrine, Ananda P. De Silva
  • Publication number: 20030230798
    Abstract: An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements (340) sealed to a MEMS device die array (300) to produce a sealed MEMS device package array (330). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.
    Type: Application
    Filed: June 12, 2002
    Publication date: December 18, 2003
    Inventors: Jong-Kai Lin, William H. Lytle, Owen Fay, Steven Markgraf, Henry G. Hughes, Craig Amrine, Ananda P. De Silva
  • Patent number: 6310403
    Abstract: A method of manufacturing components includes providing a substrate (110, 531, 631, 700) having a first coefficient of thermal expansion (CTE), having a first surface (111), and supporting a first plurality of interconnects located over the first surface in a first predetermined pattern. The method also includes providing another substrate (190) having a second CTE, having a second surface (195), and supporting a second plurality of interconnects located over the second surface in a second predetermined pattern. The method further includes assembling together the two substrates at a first temperature outside of a temperature range of approximately 25 to 30° C.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: October 30, 2001
    Assignee: Motorola, Inc.
    Inventors: Chunsheng Zhang, Jong-Kai Lin, Scott E. Lindsey, Yifan Guo, Li Li
  • Patent number: 6022761
    Abstract: A method for connecting substrates includes using an adhesive interposer structure (11) to bond a semiconductor device (26) to a substrate (18). The adhesive interposer structure (11) includes a non-conductive adhesive laminant (12) and conductive adhesive bumps (13). The conductive adhesive bumps (13) provide a conductive path between conductive bumps (27) on the semiconductor device (26) and conductive metal pads (21) located on the substrate (18). In an alternative embodiment, a conductive adhesive material (34) is screen or stencil printed into vias (39) located on a printed circuit board (38) to form conductive adhesive bumps (33). A non-conductive adhesive (52) is then screen or stencil printed onto the printed circuit board (38) adjacent the conductive adhesive bumps (33). A semiconductor die is then connected to the structure.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: February 8, 2000
    Assignee: Motorola, Inc.
    Inventors: Melissa E. Grupen-Shemansky, Jong-Kai Lin, Theodore G. Tessier
  • Patent number: 5674780
    Abstract: A method of forming an electrically conductive polymer bump (22) over an aluminum electrode (21) produces low contact resistance for an interconnect structure (24). Aluminum oxide is first removed from the aluminum electrode (21). Tiron and palladium are subsequently bonded to the fresh surface of the aluminum electrode (21). Finally, the electrically conductive polymer bump (22) is formed over the aluminum electrode (21). The Tiron and palladium improve the electrical contact between the conductive polymer bump (22) and the aluminum electrode (21) thereby reducing the contact resistance. The Tiron also inhibits corrosion of the aluminum electrode (21) and enhances the conductivity by catalytically shrinking the cyanate ester conductive bump.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: October 7, 1997
    Assignee: Motorola, Inc.
    Inventors: William H. Lytle, Treliant Fang, Jong-Kai Lin, Ravinder K. Sharma, Naresh C. Saha
  • Patent number: 5587342
    Abstract: Interconnect bumps are formed on a circuit substrate using printing or dispensing techniques with a wet photoresist layer as a mask. A conductive paste is disposed in openings of a wet photoresist layer. The conductive paste is at least partially cured before the wet photoresist layer is removed. Alternatively, the wet photoresist layer may remain if it is a photo-imagable polyimide.
    Type: Grant
    Filed: April 3, 1995
    Date of Patent: December 24, 1996
    Assignee: Motorola, Inc.
    Inventors: Jong-Kai Lin, William H. Lytle, Ravichandran Subrahmanyan