Abstract: A high-speed multi-stage voltage comparator is provided. The multi-stage voltage comparator is configured to eliminate offset from outputs of preamplifiers through respective offset-cancellation switches, and to reset the outputs of the preamplifiers through respective reset switches to reduce an output recovery time. Thus, the multi-stage voltage comparator operates with high accuracy and at a high speed, so that it can be usefully applied to an analog-to-digital converter (ADC), and particularly, a high-speed successive approximation register ADC (SAR ADC).

Abstract: Provided is a low voltage frequency synthesizer using a boosting method for a power supply voltage of a charge pump. The low voltage frequency synthesizer includes a phase/frequency detector (PFD) that receives and compares a reference frequency and a feedback frequency to output a comparison signal, a charge pump that receives the comparison signal to output a current corresponding to the comparison signal, a low-pass filter (LPF) that generates a voltage corresponding to the output current of the charge pump, a voltage controlled oscillator (VCO) that receives the voltage of the LPF, amplifies the voltage to generate a boosting voltage, and outputs a frequency corresponding to the received voltage, and a DC converter that receives the boosting voltage of the VCO, converts the boosting voltage into a DC voltage, and applies the DC voltage as a power supply voltage of the charge pump.

Abstract: Provided is a read-out circuit that is connected to a microphone and configured to linearly amplify a current signal generated by the microphone and output the amplified current signal. The read-out circuit includes an amplification unit and a feedback resistor. The amplification unit has an amplification gain between 0 and 1. The feedback resistor is connected between input and output terminals of the amplification unit. As the amplification gain of the amplification unit becomes closer to 1, an input impedance becomes higher. A preamp of the read-out circuit can have a high input impedance due to the amplification gain, and the read-out circuit can be manufactured using a CMOS process.

Abstract: Provided are a gain control device and an amplifier using the gain control device. The gain control device includes a first input resistance unit having a first variable resistor whose resistance is linearly variable and a first fixed resistor respectively receiving a first input signal and a second input signal having a sign different from the first input signal and outputting current through a first output terminal, and a second input resistance unit having a second fixed resistor and a second variable resistor whose resistance is linearly variable respectively receiving the first input signal and the second input signal and outputting current through a second output terminal. Since the gain control device can separately perform dB-linear gain control, it is easily combined with a circuit, such as a continuous-time sigma-delta modulator (SDM), a continuous-time filter, and a continuous-time analog-to-digital converter (ADC), and enables miniaturization and low power consumption.

Abstract: A multi-stage dual successive approximation register analog-to-digital converter (SAR ADC) and a method of performing analog-to-digital conversion using the same are provided. The multi-stage dual SAR ADC includes: a plurality of SAR ADC stages for converting an analog input voltage into a predetermined bit digital signal, each SAR ADC stage being serially connected to one another and including two SAR ADCs; and at least one residue amplifier respectively connected between every two successive SAR ADC stages, amplifying residue voltage output from a previous SAR ADC stage to output the amplified residue voltage to a next SAR ADC stage. The two SAR ADCs of the previous SAR ADC stage share the residue amplifier.

Abstract: Provided are a switching circuit and a small-size high-efficiency direct current-to-direct current (DC-DC) converter for portable devices including the same. Using dynamic threshold-complementary metal oxide semiconductor (DT-CMOS) transistors having dynamic threshold voltages as a switching device, the switching circuit maintains a low threshold voltage in a normal mode to improve current drivability while reducing conduction loss, and maintains a high threshold voltage in a standby mode to minimize power consumption. When the switching circuit is employed in a DC-DC converter, power conversion efficiency can be improved by reducing conduction loss in the normal mode, and power consumption can be minimized in the standby mode. Consequently, the DC-DC converter can maximize a use time of a battery of a portable device and can be useful in power supplies of portable devices that are gradually being miniaturized.

Abstract: A successive approximation register (SAR) analog-digital converter (ADC) and a method of driving the same are provided. The SAR ADC includes a first converting unit including a bit capacitor array corresponding to the number of bits and a correction capacitor array, a comparator outputting a high or low voltage corresponding to each capacitor according to an output voltage of the converting unit, and a correction unit correcting the output of the bit capacitor according to the output of the correction capacitor array among the high or low output of the comparator. Therefore, two bits having the same capacitance as a least significant bit (LSB) enable a digital output error to be corrected, so that a spurious free dynamic range (SFDR) of the signal converter is increased, and a signal to noise and distortion ratio (SNDR) of an output signal is improved.

Abstract: Provided are a method of algorithmic analog-to-digital conversion and an algorithmic Analog-to-Digital Converter (ADC). The algorithmic ADC includes a Multiplying Digital-to-Analog Converter (MDAC). The MDAC includes a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal, a subtractor for calculating a difference between the signal output from the DAC and an analog signal input from a first Sample and Hold Amplifier (SHA), an amplifier for amplifying the difference, a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit, a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit, and a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit.

Abstract: Provided is a switched capacitor circuit which prevents leakage current by equalizing voltages at nodes where leakage current tends to flow in a sampling mode, and prevents errors in an output signal by minimizing voltage drop caused by leakage current in an integrating mode.

Abstract: Provided is a switched-capacitor variable gain amplifier having high voltage gain linearity. According to the above amplifier, a sampling capacitor is shared and used at a sampling phase and an amplification phase, and thus a voltage gain error caused by capacitor mismatch can be reduced. Also, using a unit capacitor array enables circuit design and layout to be simplified. Further, in the amplifier, a voltage gain can be easily controlled to be more or less than 1, as necessary, and power consumption and kT/C noise can be reduced by a feedback factor that is relatively large, so that gain amplification performance can be improved.

Abstract: Provided is an algorithmic analog-to-digital converter (ADC). In the algorithmic ADC, the number of preprocessing amplifiers used in a flash ADC is reduced by sharing the preprocessing amplifiers in the flash ADC, and thus chip size can be reduced. In addition, power consumption can be reduced by dynamically decreasing the bandwidth of an operational amplifier included in a multiplying digital-to-analog converter (MDAC) according to a required resolution.

Abstract: Provided is a band-gap reference voltage generator for low-voltage operation and high precision. The band-gap reference voltage generator minimizes voltage drop by connecting resistors in parallel to bipolar transistors, and cancels temperature dependence by properly adjusting a resistor of an output stage, so that it can provide a stable reference voltage that is unaffected by a change in temperature in spite of a low power supply voltage. Further, the band-gap reference voltage generator minimizes variation of the reference voltage caused by offset noise by switching of input and output voltages at input and output stages of a feedback amplifier, so that it can provide a precise reference voltage.

Abstract: Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

Abstract: A multi-stage Successive Approximation Register Analog-to-Digital Converter (SAR ADC) and an analog-to-digital converting method using the same are provided. The multi-stage SAR ADC connects small-size and low-power SAR ADCs in multiple stages, thereby reducing a whole chip size and power consumption. The analog-to-digital converting method simultaneously performs analog-to-digital conversions in the SAR ADCs connected in the multiple stages, thereby reducing an analog-to-digital conversion time and maintaining an operating rate of several tens of MHz to several hundreds of MHz similar to that of a pipeline ADC.

Abstract: Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.

Abstract: A band-gap reference voltage generator is provided. N-channel metal oxide semiconductor (NMOS) transistors are respectively connected to bipolar transistors in parallel. A Complementary To Absolute Temperature (CTAT) voltage that is inversely proportional to absolute temperature is reduced by a threshold voltage of the NMOS transistor. A weight for a temperature coefficient of a Proportional To Absolute Temperature (PTAT) voltage that is directly proportional to absolute temperature is reduced and a resistance ratio for a temperature coefficient of 0 is reduced by about ½, thereby miniaturizing the band-gap reference voltage generator. A reference voltage lower than or equal to 1 V can be provided by resistors respectively connected to the bipolar transistors in parallel.

Abstract: Provided are a pipeline Analog-to-Digital Converter (ADC) without a front-end Sample-and-Hold Amplifier (SHA) and a method of controlling the same. The method includes the steps of: simultaneously sampling, at an ADC and a residual signal generator included in a first stage, an analog input signal and respectively generating a first sampling value and a second sampling value; holding, at the residual signal generator, the second sampling value, and simultaneously amplifying and converting, at the ADC, the first sampling value into a corresponding digital code; and generating, at the residual signal generator, a residual signal using the digital code. The pipeline ADC and method of controlling the same minimize sampling mismatch caused by removing a front-end SHA, thereby ensuring stable performance without a front-end SHA. Since a front-end SHA is not used, it is possible to reduce chip size and power consumption, and improve the performance of the ADC.

Abstract: Provided is a band-gap reference voltage generator for low-voltage operation and high precision. The band-gap reference voltage generator minimizes voltage drop by connecting resistors in parallel to bipolar transistors, and cancels temperature dependence by properly adjusting a resistor of an output stage, so that it can provide a stable reference voltage that is unaffected by a change in temperature in spite of a low power supply voltage. Further, the band-gap reference voltage generator minimizes variation of the reference voltage caused by offset noise by switching of input and output voltages at input and output stages of a feedback amplifier, so that it can provide a precise reference voltage.

Abstract: Provided are a method of algorithmic analog-to-digital conversion and an algorithmic Analog-to-Digital Converter (ADC). The algorithmic ADC includes a Multiplying Digital-to-Analog Converter (MDAC). The MDAC includes a Digital-to-Analog Converter (DAC) for converting a first digital signal into an analog signal, a subtractor for calculating a difference between the signal output from the DAC and an analog signal input from a first Sample and Hold Amplifier (SHA), an amplifier for amplifying the difference, a first capacitor unit connected with an output end of the first SHA and an input end of the amplifier through a first switching unit, a second capacitor unit connected with the input end and an output end of the amplifier through a second switching unit, and a third capacitor unit connected with the input end and the output end of the amplifier through a third switching unit.

Abstract: Provided is a switched-capacitor variable gain amplifier having high voltage gain linearity. According to the above amplifier, a sampling capacitor is shared and used at a sampling phase and an amplification phase, and thus a voltage gain error caused by capacitor mismatch can be reduced. Also, using a unit capacitor array enables circuit design and layout to be simplified. Further, in the amplifier, a voltage gain can be easily controlled to be more or less than 1, as necessary, and power consumption and kT/C noise can be reduced by a feedback factor that is relatively large, so that gain amplification performance can be improved.