Patents by Inventor Jong-min Baek

Jong-min Baek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190244896
    Abstract: A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.
    Type: Application
    Filed: June 14, 2018
    Publication date: August 8, 2019
    Inventors: Eui Bok LEE, Jong Min BAEK, Sang Hoon AHN, Hyeok Sang OH
  • Publication number: 20190198342
    Abstract: Provided herein is a method of forming micropatterns, including: forming an etching target film on a substrate; forming a photosensitivity assisting layer on the etching target film, the photosensitivity assisting layer being terminated with a hydrophilic group; forming an adhesive layer on the photosensitivity assisting layer, the adhesive layer forming a covalent bond with the hydrophilic group; forming a hydrophobic photoresist film on the adhesive layer; and patterning the photoresist film.
    Type: Application
    Filed: December 27, 2018
    Publication date: June 27, 2019
    Inventors: SANG-SHIN JANG, JONG-MIN BAEK, HOON-SEOK SEO, EUI-BOK LEE, SUNG-JIN KANG, VIETHA NGUYEN, DEOK-YOUNG JUNG, SANG-HOON AHN, HYEOK-SANG OH, WOO-KYUNG YOU
  • Publication number: 20190189744
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 20, 2019
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20190181088
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.
    Type: Application
    Filed: July 19, 2018
    Publication date: June 13, 2019
    Inventors: Eui Bok Lee, Deok Young JUNG, Sang Bom KANG, Doo-Hwan PARK, Jong Min BAEK, Sang Hoon AHN, Hyeok Sang OH, Woo Kyung YOU
  • Patent number: 10315964
    Abstract: According to the present invention, a deuterium-substituted marker for fuel is synthesized through substitution with deuterium so as to have structurally and chemically similar properties to those of a molecule configuring fuel oil. A molecule of the deuterium-substituted marker is significantly similar to the conventional molecule configuring the fuel oil, which may prevent illegal removal of the marker by the fake oil manufacturers. According to the present invention, it is able to pursue public safety and environmental protection from fake oil products, and to prevent national tax evasion, by preventing the illegal mixing of fuel oil to secure a legal distribution of the oil market according to the present invention.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: June 11, 2019
    Assignee: Korea Institute of Petroleum Management
    Inventors: Young-Kwan Lim, Hee-Yeon Baek, Kyoung-Heum Lee, Seung-Hyun Ryu, Ju Min Youn, Jong Ryeol Kim, In Ha Hwang, Jong Han Ha
  • Publication number: 20190164295
    Abstract: Provided are a system and method for simultaneously reconstructing an initial three-dimensional (3D) trajectory and velocity of an object by using single camera images. The system for simultaneously reconstructing an initial 3D trajectory and velocity of an object by using single camera images includes a receiver configured to receive 3D world coordinate information of a starting point of an object and object-captured image information of a single camera, a two-dimensional (2D) coordinate acquisition unit configured to acquire 2D image coordinates of the object from the object-captured image information, and a reconstructor configured to simultaneously reconstruct an initial 3D velocity and trajectory of the object by applying a 3D motion equation to the 2D image coordinates and depth information from the single camera to the object.
    Type: Application
    Filed: June 25, 2018
    Publication date: May 30, 2019
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jong Sung KIM, Myung Gyu KIM, Woo Suk KIM, Seong Min BAEK, Sang Woo SEO, Sung Jin HONG
  • Patent number: 10304734
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
  • Publication number: 20190148289
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.
    Type: Application
    Filed: May 23, 2018
    Publication date: May 16, 2019
    Inventors: Hoon Seok SEO, Jong Min BAEK, Su Hyun BARK, Sang Hoon AHN, Hyeok Sang OH, Eui Bok LEE
  • Publication number: 20190148167
    Abstract: An etching gas mixture, a method of forming a pattern using the etching gas mixture, and a method of manufacturing an integrated circuit device using the etching gas mixture, the etching gas mixture including a C1-C3 perfluorinated alkyl hypofluorite; and a C1-C10 organosulfur compound that includes a C—S bond in the compound.
    Type: Application
    Filed: September 27, 2018
    Publication date: May 16, 2019
    Applicant: Wonik Materials
    Inventors: Do-hoon KIM, Tae-hyung KIM, Jong-min BAEK, Han-dock SONG
  • Publication number: 20190139813
    Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.
    Type: Application
    Filed: January 8, 2019
    Publication date: May 9, 2019
    Inventors: Sang-Shin JANG, Woo-Kyung YOU, Kyu-Hee HAN, Jong-Min BAEK, Viet Ha NGUYEN, Byung-Hee KIM
  • Patent number: 10217820
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20190043803
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.
    Type: Application
    Filed: December 13, 2017
    Publication date: February 7, 2019
    Inventors: Woo Kyung YOU, Eui Bok LEE, Jong Min BAEK, Su Hyun BARK, Jang Ho LEE, Sang Hoon AHN, Hyeok Sang OH
  • Patent number: 10199263
    Abstract: A semiconductor device includes a first insulating interlayer on a first region of a substrate and a second insulating interlayer on a second region of the substrate, a plurality of first wiring structures on the first insulating interlayer, the first wiring structures being spaced apart from each other, a plurality of second wiring structures filling a plurality of trenches on the second insulating interlayer, respectively, an insulation capping structure selectively on a surface of the first insulating interlayer between the first wiring structures and on a sidewall and an upper surface of each of the first wiring structures, the insulation capping structure including an insulating material, a third insulating interlayer on the first and second wiring structures, and an air gap among the first wiring structures under the third insulating interlayer.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Shin Jang, Woo-Kyung You, Kyu-Hee Han, Jong-Min Baek, Viet Ha Nguyen, Byung-Hee Kim
  • Publication number: 20190019759
    Abstract: A semiconductor device includes an element layer, a plurality of first interconnect lines on the element layer, a first insulation layer including carbon having a uniform concentration distribution between the first interconnect lines, a plurality of second interconnect lines spaced from the first interconnect lines, and a second insulation layer between the second interconnect lines. An air spacing is included between the second interconnect lines.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 17, 2019
    Inventors: Sang Hoon AHN, Tae Soo KIM, Jong Min BAEK, Woo Kyung YOU, Thomas OSZINDA, Byung Hee KIM, Nae In LEE
  • Publication number: 20180330987
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Inventors: WOO KYUNG YOU, JONG MIN BAEK, SANG SHIN JANG, BYUNG HEE KIM, VIETHA NGUYEN, NAE IN LEE, WOO JIN LEE, EUN JI JUNG, KYU HEE HAN
  • Patent number: 10128148
    Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Viet Ha Nguyen, Nae In Lee, Thomas Oszinda, Byung Hee Kim, Jong Min Baek, Tae Jin Yim
  • Patent number: 10096549
    Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung Hee Kim, Thomas Oszinda, Deok Young Jung, Jong Min Baek, Tae Jin Yim
  • Patent number: 10062609
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
  • Patent number: 10008407
    Abstract: A method of forming a semiconductor device can include forming an insulation layer using a material having a composition selected to provide resistance to subsequent etching process. The composition of the material can be changed to reduce the resistance of the material to the subsequent etching process at a predetermined level in the insulation layer. The subsequent etching process can be performed on the insulation layer to remove an upper portion of the insulation layer above the predetermined level and leave a lower portion of the insulation layer below the predetermined level between adjacent conductive patterns extending through the lower portion of the insulation layer. A low-k dielectric material can be formed on the lower portion of the insulation layer between the adjacent conductive patterns to replace the upper portion of the insulation layer above the predetermined level.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Jin Lee, Byung-Hee Kim, Sang-Hoon Ahn, Woo-Kyung You, Jong-Min Baek, Nae-In Lee
  • Patent number: 9991203
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: June 5, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Rak-Hwan Kim, Byung-Hee Kim, Jin-Nam Kim, Jong-Min Baek, Nae-In Lee, Eun-Ji Jung