Abstract: A semiconductor memory device including an antifuse cell array and a spare antifuse cell array are provided. An antifuse cell array includes a first set of antifuse cells arranged in a first direction and each one of the first set of antifuse cells is connected to a corresponding one of first through nth word lines. The spare antifuse cell array includes a first spare set of antifuse cells arranged in the first direction and each one of the first spare set of antifuse cells is connected to a corresponding one of first through kth spare word lines. A first operation control circuit is configured to program antifuses of the antifuse cell array and the spare antifuse cell array, and to read a status of each of the antifuses. The first operation control circuit is commonly connected to the first set of antifuse cells and the first spare set of antifuse cells.

Abstract: A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.

Abstract: A method and apparatus for inputting letters by combining basic elements obtained by separating and symbolizing strokes of letters, so as to provide excellent letter intuitiveness and recognition. According to the present invention, a letter may be input by pressing one of or sequentially pressing two of keys to which basic elements u, I, n, ?, l, ?, , †, , _, and o obtained by separating and symbolizing strokes of letters are assigned, and letters may be rapidly and conveniently input by minimizing key pressing paths.

Abstract: A semiconductor device includes a bit line connected to a plurality of memory cells in a memory block and a sense amplifier having a first node connected to the bit line and a second node, which is not connected to any bit line. The second node has a capacitive load less than that of the bit line. The sense amplifier amplifies a first data using a voltage difference between the first node and the second node caused by a charge sharing operation, and a second data using a capacitive mismatch between the first node and the second node.

Abstract: A method of forming a metal layer pattern comprises forming an interlayer insulating layer on a semiconductor substrate, forming a metal layer on the interlayer insulating layer, forming a mask pattern to expose a predetermined area of the metal layer, and forming a metal layer pattern by dry etching the exposed predetermined area of the metal layer with a substrate bias power of about 5 W to about 40 W.