Patents by Inventor Jong Moon Park
Jong Moon Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20130087884Abstract: Disclosed is a silicon interposer that can reduce the entire area of a semiconductor package and increase the degree of integration by forming inductors at a lower part in addition to an upper part of a silicon substrate. The silicon interposer includes a silicon substrate, an upper inductor layer formed at the upper part of the silicon substrate and a lower inductor layer formed at the lower part of the silicon substrate.Type: ApplicationFiled: June 11, 2012Publication date: April 11, 2013Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Hyun-Cheol BAE, Kwang-Seong CHOI, Jong Tae Moon, Jong-Moon PARK
-
Publication number: 20120098057Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.Type: ApplicationFiled: September 9, 2011Publication date: April 26, 2012Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sang Gi KIM, Jin-Gun Koo, Seong Wook Yoo, Jong-Moon Park, Jin Ho Lee, Kyoung Il Na, Yil Suk Yang, Jongdae Kim
-
Patent number: 7994553Abstract: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes arType: GrantFiled: August 20, 2008Date of Patent: August 9, 2011Assignee: Electronics and Telecommunications Research InstituteInventors: Yong Sun Yoon, Kun Sik Park, Jong Moon Park, Bo Woo Kim, Jin Yeong Kang
-
Publication number: 20110034872Abstract: A liquid delivery apparatus for the intrathecal delivery of one or more medications to a patient is disclosed. The liquid delivery apparatus generally includes a liquid reservoir, a liquid metering unit fluidly connected to the liquid reservoir, and a catheter delivery tube fluidly connected to the liquid metering unit. Preferably, the liquid delivery apparatus includes two or more liquid reservoirs. In various embodiments, the liquid reservoir includes a deformable balloon and a compressive sleeve spring as a pressure source, the liquid metering unit is a piezoelectrically actuated microvalve, and/or diagnostic sensors are included in the apparatus. The disclosed apparatus are compact, volume-efficient, energy-efficient, capable of delivering accurate fluid volumes, and address problems associated with multi-medication therapies. Methods of operating the liquid delivery apparatus are also disclosed.Type: ApplicationFiled: December 8, 2008Publication date: February 10, 2011Applicant: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Srinivas Chiravuri, Allan Evans, Yogesh B. Gianchandani, Jong Moon Park
-
Patent number: 7855366Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.Type: GrantFiled: April 29, 2008Date of Patent: December 21, 2010Assignee: Electronics and Telecommunications Research InstituteInventors: Kun Sik Park, Yong Sun Yoon, Bo Woo Kim, Jin Yeong Kang, Jong Moon Park, Seong Wook Yoo
-
Publication number: 20090321641Abstract: A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.Type: ApplicationFiled: April 29, 2008Publication date: December 31, 2009Applicant: Electronics and Telecommunications Research InstituteInventors: Kun Sik PARK, Yong Sun YOON, Bo Woo KIM, Jin Yeong KANG, Jong Moon PARK, Seong Wook YOO
-
Publication number: 20090146238Abstract: A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes arType: ApplicationFiled: August 20, 2008Publication date: June 11, 2009Applicant: Electronics and Telecommunications Research InstituteInventors: Yong Sun Yoon, Kun Sik Park, Jong Moon Park, Bo Woo Kim, Jin Yeong Kang
-
Patent number: 7190432Abstract: Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.Type: GrantFiled: October 13, 2005Date of Patent: March 13, 2007Assignee: Electronics and Telecommunications Research InstituteInventors: Sang Gi Kim, Ju Wook Lee, Jong Moon Park, Seong Wook Yoo, Kun Sik Park, Yong Sun Yoon, Yoon Kyu Bae, Byung Won Lim, Jin Gun Koo, Boo Woo Kim
-
Patent number: 7170044Abstract: Provided is a photodetector in which a transparent nonconductive material having an interface charge and a trapped charge is deposited on a semiconductor surface so as to form a depletion region on the surface of the semiconductor, and the depletion region is employed as an optical detecting region, thereby not only improving detection with respect to light having a wavelength of ultraviolet and blue ranges but also filtering light having a wavelength of visible and infrared ranges, and in which a fabricating process thereof is compatible with a universal silicon CMOS process.Type: GrantFiled: August 9, 2004Date of Patent: January 30, 2007Assignee: Electronics and Telecommunications Research InstituteInventors: Kun Sik Pakr, Seong Wook Yoo, Jong Moon Park, Yong Sun Yoon, Sang Gi Kim, Bo Woo Kim, Yoon Kyu Bae, Byung Won Lim, Jin Gun Koo
-
Patent number: 7141464Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possibleType: GrantFiled: July 12, 2005Date of Patent: November 28, 2006Assignee: Electronics and Telecommunications Research InstituteInventors: Jong Moon Park, Kun Sik Park, Seong Wook Yoo, Yong Sun Yoon, Sang Gi Kim, Yoon Kyu Bae, Byung Won Lim, Jin Gun Koo, Bo Woo Kim
-
Publication number: 20060109444Abstract: Provided is a wafer exposure apparatus used in a semiconductor device manufacturing process, the exposure apparatus including: a reflective mirror for reflecting light provided from a light source; an optical path changer for changing a path of the light provided from the reflective mirror; first mirrors installed at both sides of the optical path changer to change the path of the light; second mirrors installed at both sides of a material to change the path of the light; and third mirrors installed at both sides of a mask to enter the light reflected by the first mirrors to the mask and to enter the light passed through the mask into the second mirrors, whereby it is possible to continuously expose one surface, both surfaces or a specific surface of a wafer in a state that the wafer is once aligned.Type: ApplicationFiled: October 13, 2005Publication date: May 25, 2006Inventors: Sang Gi Kim, Ju Wook Lee, Jong Moon Park, Seong Wook Yoo, Kun Sik Park, Yong Sun Yoon, Yoon Kyu Bae, Byung Won Lim, Jin Gun Koo, Boo Woo Kim
-
Publication number: 20060079030Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possibleType: ApplicationFiled: July 12, 2005Publication date: April 13, 2006Inventors: Jong Moon Park, Kun Sik Park, Seong Wook Yoo, Yong Sun Yoon, Sang Gi Kim, Yoon Kyu Bae, Byung Won Lim, Jin Gun Koo, Bo Woo Kim
-
Patent number: 5964629Abstract: To form a silicon tip having an undercut, a photoresist pattern having a vertical profile or a positive profile is formed on a silicon substrate and an under-cuted isotropic etching process is then performed using the photoresist pattern as a mask. First and second insulation films are formed on the silicon tip and the silicon substrate except for the silicon tip. The first insulation film is then separated from the second insulation film.Type: GrantFiled: November 21, 1996Date of Patent: October 12, 1999Assignee: Electronics and Telecommunications Research InstituteInventors: Jong Moon Park, Jin Keon Ku, Ki Hong Kim, Yeong Cheol Hyeon, Min Park
-
Patent number: 5887455Abstract: A washing machine includes an external cabinet, an outer tub installed inside the external cabinet, a spin basket rotatably installed inside the outer tub and a plurality of suspension units for suspending the outer tub with respect to the external cabinet. Each of the suspension units comprises: a suspension bar for connecting the outer tub to the external cabinet; a main damper combined with one end of the suspension bar; and an auxiliary damper combined with the one end of the suspension bar, adjacent to said main damper. Accordingly, vibrations and noises of the outer tub can be reduced effectively.Type: GrantFiled: May 22, 1997Date of Patent: March 30, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Do Weon Kim, Jong Moon Park, Sung Jae Shin
-
Patent number: 5769679Abstract: In a method, a film for a gate electrode, exposed through the sidewall of a trench, is thermally treated to grow a thermal oxide film which is, then, removed at the lateral side of the gate electrode, to spatially separate the gate electrode from the gate insulating film in space. This method precisely controls the thermal oxide film formed at the lateral side of the gate electrode, so that the distance between the gate electrode and the electron emission cathode can be accurately adjusted. The electron emission cathodes are homogeneous in shape. Also, the reliability of the display can be improved since a silicide metal is formed on the electron emission cathodes.Type: GrantFiled: September 18, 1996Date of Patent: June 23, 1998Assignee: Electronics and Telecommunications Research InstituteInventors: Jong-Moon Park, Yeong-Cheol Hyeon, Kee-Soo Nam