Patents by Inventor Jong-Seo Hong

Jong-Seo Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120052667
    Abstract: A method of fabricating a semiconductor device includes forming gate patterns on a substrate, forming spacers on sidewalls of the gate patterns, forming a first capping insulation layer pattern on the gate patterns and the spacers, forming a second capping insulation layer pattern on the first capping insulation layer pattern, forming a passivation layer pattern filling contact holes between the gate patterns, removing the second capping insulation layer pattern while protecting the spacers using the passivation layer pattern, removing the passivation layer pattern to expose a top surface of the substrate, forming a silicide forming metal film on the surface of the substrate, and forming silicide patterns on the exposed top surface of the substrate.
    Type: Application
    Filed: August 8, 2011
    Publication date: March 1, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-Tae Kim, Jong-Seo Hong
  • Publication number: 20120052647
    Abstract: A method for fabricating a semiconductor device is disclosed. One embodiment of the method includes forming a dummy gate pattern on a substrate, forming an interlayer dielectric film that covers the dummy gate pattern, exposing a top surface of the dummy gate pattern, selectively removing the dummy gate pattern to form a first gate trench, forming a sacrificial layer pattern over a top surface of the substrate in the first gate trench, the sacrificial layer pattern leaving a top portion of the first gate trench exposed, increasing an upper width of the exposed top portion of the first gate trench to form a second gate trench, and removing the sacrificial layer pattern in the second gate trench, and forming a non-dummy gate pattern in the second gate trench.
    Type: Application
    Filed: July 29, 2011
    Publication date: March 1, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-Tae Kim, Jong-Seo Hong, Tae-Han Kim
  • Publication number: 20110117715
    Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
    Type: Application
    Filed: January 20, 2011
    Publication date: May 19, 2011
    Inventors: Jong-Seo Hong, Jeong-Sic Jeon, Chun-Suk Suh, Yoo-Sang Hwang
  • Patent number: 7888724
    Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Jong-Seo Hong, Jeong-Sic Jeon, Chun-Suk Suh, Yoo-Sang Hwang
  • Patent number: 7851354
    Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: December 14, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-woo Seo, Jong-seo Hong, Tae-hyuk Ahn, Jeong-sic Jeon, Jun-sik Hong, Young-sun Cho
  • Patent number: 7682778
    Abstract: Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Woo Seo, Tae-Hyuk Ahn, Jong-Seo Hong
  • Patent number: 7648875
    Abstract: A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: January 19, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Seo Hong, Jung-Woo Seo, Jun-Sik Hong, Jeong-Sic Jeon
  • Patent number: 7511328
    Abstract: A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: March 31, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Woo Seo, Tae-Hyuk Ahn, Jong-Seo Hong
  • Publication number: 20090068809
    Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
    Type: Application
    Filed: November 10, 2008
    Publication date: March 12, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-woo SEO, Jong-seo HONG, Tae-hyuk AHN, Jeong-sic JEON, Jun-sik HONG, Young-sun CHO
  • Patent number: 7462899
    Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: December 9, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-woo Seo, Jong-seo Hong, Tae-hyuk Ahn, Jeong-sic Jeon, Jun-sik Hong, Young-sun Cho
  • Publication number: 20060222966
    Abstract: Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.
    Type: Application
    Filed: January 31, 2006
    Publication date: October 5, 2006
    Inventors: Jung-Woo Seo, Tae-Hyuk Ahn, Jong-Seo Hong
  • Publication number: 20060186479
    Abstract: A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
    Type: Application
    Filed: February 15, 2006
    Publication date: August 24, 2006
    Inventors: Jung-woo Seo, Jong-seo Hong, Tae-hyuk Ahn, Jeong-sic Jeon, Jun-sik Hong, Young-sun Cho
  • Patent number: 7074725
    Abstract: An improved method of manufacturing a capacitor on a semiconductor substrate is disclosed. A portion of an insulation film on a semiconductor substrate is etched to form a first opening in the insulation film. A passivation film is formed on the insulation film and within the first opening thereof. A portion of the passivation film on a bottom of the first opening is thinner than portions of the passivation film on the insulation film and on a sidewall of the first opening. The passivation film is etched to expose the bottom of the first opening.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: July 11, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Sik Hong, Young-Ki Hong, Tae-Hyuk Ahn, Jong-Seo Hong
  • Publication number: 20060146595
    Abstract: A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.
    Type: Application
    Filed: January 6, 2006
    Publication date: July 6, 2006
    Inventors: Jong-Seo Hong, Jung-Woo Seo, Jun-Sik Hong, Jeong-Sic Jeon
  • Publication number: 20060138561
    Abstract: A semiconductor device and method of manufacturing the same having pad extending parts, the semiconductor device includes an isolation layer that defines an active region and a gate electrode which traverses the active region. A source region is provided in the active region at one side of the gate electrode, and a drain region is provided in the active region at a second side of the gate electrode. A first interlayer insulating layer covers the semiconductor substrate. A source landing pad is electrically connected to the source region, and a drain landing pad is electrically connected to the drain region. A pad extending part is laminated on one or more of the source landing pad and the drain landing pad. The pad extending part has an upper surface located in a plane above a plane corresponding to the upper surfaces of the source landing pad and the drain landing pad.
    Type: Application
    Filed: November 8, 2005
    Publication date: June 29, 2006
    Inventors: Jung-Woo Seo, Tae-Hyuk Ahn, Jong-Seo Hong
  • Publication number: 20060138513
    Abstract: A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
    Type: Application
    Filed: December 22, 2005
    Publication date: June 29, 2006
    Inventors: Jong-Seo Hong, Jeong-Sic Jeon, Chun-Suk Suh, Yoo-Sang Hwang
  • Publication number: 20040063287
    Abstract: In a semiconductor device capable of reducing operation fails and a method of manufacturing the same, gate structures and source/drain regions are formed on a semiconductor substrate. Nitride spacers are formed on both sidewalls of each of the gate structures. A first insulating interlayer is formed to cover the gate structures. Source pad electrodes are formed in each of the first contact holes and connected to the exposed source regions. A second insulating interlayer is formed on the first insulating interlayer. Metal lines for signal transmission are formed on the second insulating interlayer so as to make direct contact with the drain region of each group to electrically connect the drain regions with each other, while being isolated from the source pad electrodes.
    Type: Application
    Filed: May 30, 2003
    Publication date: April 1, 2004
    Inventors: Dong-Hyun Kim, Tae-Hyuk Ahn, Jong-Seo Hong, Min-Ho Kim
  • Publication number: 20040048475
    Abstract: An improved method of manufacturing a capacitor on a semiconductor substrate is disclosed. A portion of an insulation film on a semiconductor substrate is etched to form a first opening in the insulation film. A passivation film is formed on the insulation film and within the first opening thereof. A portion of the passivation film on a bottom of the first opening is thinner than portions of the passivation film on the insulation film and on a sidewall of the first opening. The passivation film is etched to expose the bottom of the first opening.
    Type: Application
    Filed: August 14, 2003
    Publication date: March 11, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jun-Sik Hong, Young-Ki Hong, Tae-Hyuk Ahn, Jong-Seo Hong
  • Patent number: 5476807
    Abstract: A method for forming a fine pattern, e.g., for forming the storage electrodes of the capacitors of the memory cells of semiconductor memory devices, which includes the steps of depositing a mask layer on the layer to be patterned, depositing a photoresist layer on the mask layer, patterning the photoresist layer, to thereby form a photoresist pattern, anisotropically etching the mask layer, using the photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of the photoresist pattern and the mask layer pattern, and, etching the layer to be patterned using the composite layer and the etch by-products as an etching mask, to thereby form a fine pattern. The mask layer is made of a material, e.g., a high-temperature oxide, having different physical properties than that of the photoresist. Further, the anisotropic etching process is preferably carried out by means of a plasma etching process using a mixture of CF.
    Type: Grant
    Filed: April 14, 1994
    Date of Patent: December 19, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-hyun Lee, Jong-seo Hong, Hyoung-sub Kim, Jae-ho Kim, Min-seog Han
  • Patent number: 5252177
    Abstract: A method for forming a multilayer wiring, in a method for manufacturing a semiconductor device, is disclosed. The method comprises: forming a contact hole 33 on the surface of a conductive layer 29 by a photolithography, removing a photoresist by using plasma ashing at a predetermined temperature, pressure and amount of oxygen per unit cubic, and simultaneously forming a protective layer 35 consisting of a oxide layer on the surface of the exposed conductive layer. Thus, damage of the surface of wiring caused by the chemical reaction of an organic solvent and water in the subsequent process thereof, is prevented, to provide high density and high speed semiconductor integrated circuit whose electrode characteristics between two wiring layers is improved.
    Type: Grant
    Filed: July 29, 1991
    Date of Patent: October 12, 1993
    Assignee: SamSung Electronics Co., Ltd.
    Inventors: Jong-Seo Hong, Jin-Hong Kim, Jung-In Hong