Abstract: Embodiments of methods for testing three-dimensional memory devices are disclosed. The method can include: applying an input signal to a first conductive pad of the memory device by a first probe of a probe card; transmitting the input signal through the first conductive pad, a first TAC, a first interconnect structure passing through a bonding interface of the memory device, at least one of a memory array contact and a test circuit to a test structure; receiving an output signal through a second interconnect structure passing through the bonding interface, a second TAC, at least one of the memory array contact and the test circuit from the test structure; measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and determining a characteristic of the test structure based on the input signal and the output signal.

Abstract: Embodiments of methods for testing three-dimensional memory devices are disclosed. The method can include: applying an input signal to a first conductive pad of the memory device by a first probe of a probe card; transmitting the input signal through the first conductive pad, a first TAC, a first interconnect structure passing through a bonding interface of the memory device, at least one of a memory array contact and a test circuit to a test structure; receiving an output signal through a second interconnect structure passing through the bonding interface, a second TAC, at least one of the memory array contact and the test circuit from the test structure; measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and determining a characteristic of the test structure based on the input signal and the output signal.

Abstract: Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.

Abstract: Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.

Abstract: A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

Abstract: A serial flash memory is provided with multiple configurable pins, at least one of which is selectively configurable for use in either single-bit serial data transfers or multiple-bit serial data transfers. In single-bit serial mode, data transfer is bit-by-bit through a pin. In multiple-bit serial mode, a number of sequential bits are transferred at a time through respective pins. The serial flash memory may have 16 or fewer pins, and even 8 or fewer pins, so that low pin count packaging such as the 8-pin or 16-pin SOIC package and the 8-contact MLP/QFN/SON package may be used. The availability of the single-bit serial type protocol enables compatibility with a number of existing systems, while the availability of the multiple-bit serial type protocol enables the serial flash memory to provide data transfer rates, in systems that can support them, that are significantly faster than available with standard serial flash memories.

Abstract: An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n? source region. A heavily doped p+ region known as a “halo” is disposed in the channel adjacent the heavily doped n+ drain. The floating gate is spaced away from the channel region by a generally thin tunnel oxide. A lightly doped source with a graded source/channel junction reduces source side CHE generation. In one variation, a thicker oxide between the source and the floating gate reduces CHE injection from the source side. A heavily doped drain with a halo implant in the channel adjacent the drain enhances drain side CHE generation.

Abstract: In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.

Abstract: A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

Abstract: In nonvolatile memory cell array, the memory cells of each sector are organized into groups of successive cells, the groups preferably being of the same size and preferably isolated from one another in both the row and column directions by a suitable isolation structure such as field dielectric or trench dielectric. Because of cell group isolation, each group of column lines may be decoded by its own relatively small program column select, which preferably is replicated in essentially identical form for all groups of column lines. While each program column select preferably is used to decode one group of column lines, larger program column selects may be used if desired to decode two or more groups of column lines. Read column selects may decode one or more groups of column lines as desired. The number of column lines decoded may the same as or different than the number of column lines decoded.

Abstract: A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subsequent voltage pulses in the convergence signal each have a longer duration than the preceding pulse. An integrated circuit includes an array of memory cells and an erase control unit which controls the application of the convergence signal to one or more memory cells. The integrated circuit may be either serial or parallel flash EEPROM in which bulk, sector, or page mode erasing is used.

Abstract: There is disclosed a multi-step pulse generating circuit and a method of erasing a flash memory cell using the same, which can shorten the erase time for the flash memory and reduce the size of a device, in a way that it stores the information at the time when the suspense command is input during the multi-step pulse erase operation, switches it into a read mode, and resumes the erase operation from the time when the information is stored.

Abstract: A method of programming a nonvolatile semiconductor device at low power. A programming operation is performed by applying a high voltage to a gate of a selected memory cell to induce a strong electric field from a semiconductor substrate, applying a ground voltage to a drain of the selected cell and allowing a source of the selected cell to float. A desired voltage is applied to drains of nonselected memory cells not to program the nonselected memory cells. The desired voltage has half the level of the high voltage applied to the gate of the selected memory cell. Therefore, in a NOR-type flash memory, the programming operation is performed not in a hot-electron implantation manner, but in an F-N tunneling manner, so as to program a number of cells, more particularly on a page-by-page basis, at low power.

Abstract: A drain voltage pumping circuit comprising: a detection unit for outputting program control signal by detecting the number of bits for programming before programming memory cells on a memory cell array; and a drain voltage pumping unit for generating a drain voltage according to the program control signals of the detection unit.

Abstract: The present invention provides a novel nonvolatile Flash EEPROM array design which allows for array, block or sector erase capabilities. The relatively simple transistor design layout of the present invention allows small portions of the EEPROM array to be erased without affecting data stored in the remaining portion of the array. In addition, given the block structured layout of the Flash EEPROM array, adjacent blocks in the array can share transistor control circuitry, thus minimizing the size of the array. The novel nonvolatile Flash EEPROM array preferably comprises a plurality of blocks which comprise a plurality of sectors of NOR-gate transistors. Each transistor has a drain, a source, and a control gate. Preferably, the drains of each transistor in a column are electrically coupled, the control gates of each transistor in a row are electrically coupled, and the sources of all the transistors in a sector are electrically coupled.

Abstract: The present invention discloses a flash memory device, a first well and second well are formed in a substrate, a plurality of memory cell are formed in the second well and arranged in an array having a multiplicity of bit lines and word lines. Voltage is applied to the first well and second well, respectively, with time interval so that an over erasing of the memory cell and lowering of cycling characteristic can be prevented.

Abstract: The present invention provides a novel nonvolatile Flash EEPROM array design which allows for array, block or sector erase capabilities. The relatively simple transistor design layout of the present invention allows small portions of the EEPROM array to be erased without affecting data stored in the remaining portion of the array. In addition, given the block structured layout of the Flash EEPROM array, adjacent blocks in the array can share transistor control circuitry, thus minimizing the size of the array. The novel nonvolatile Flash EEPROM array preferably comprises a plurality of blocks which comprise a plurality of sectors of NOR-gate transistors. Each transistor has a drain, a source, and a control gate. Preferably, the drains of each transistor in a column are electrically coupled, the control gates of each transistor in a row are electrically coupled, and the sources of all the transistors in a sector are electrically coupled.

Abstract: This invention relates to a flash memory device capable of performing a multi bit program by sequentially supplying a data stored on a data storage circuit to a word line coupled to a select gate of a memory cell selected by a row decoder when a program bias voltage is applied to a bit line.

Abstract: A non-volatile memory access protocol that facilitates concurrent accessing operations to multiple non-volatile memory components. This approach provides significant speed advantages over prior art non-volatile protocols. Also, power consumption is reduced in comparison to prior art synchronous protocols used for volatile memory because each memory component need not be continuously selected.

Abstract: The present invention provides a method for programming and erasing a plurality of flash memory cells simultaneously while the power consumptions for those operations are significantly reduced, and the method for programming a memory cell of a flash memory device, wherein the memory cell is formed on a P-well surrounded by an N-well of a semiconductor substrate, including the steps of: applying a negative voltage to a control gate of the memory cell; applying a positive voltage to a drain of the memory cell; applying a positive voltage to the P-well, wherein the voltage is the same as or lower than the voltage applied to the drain; applying a power supply voltage to the N-well; and leaving a source of the memory cell uncoupled, wherein the steps are performed either in sequence or at random.