Abstract: A column repair circuit for a semiconductor memory having an input/output selection circuit for inputting a control signal, selecting a bit line and a bit bar line corresponding to a faulty memory cell and replacing the selected bit line and bit bar line with a spare bit line and a spare bit bar line. The input/output selection circuit includes an input stage for inputting the control signal, a spare bit line and a spare bit bar line, and a plurality of fuses each having one side connected to the input stage and other side connected to a plurality of resistors. The other side of the resistors are connected to ground for outputting the output signals. The input/output selection circuit further has a plurality of n-channel MOSFETs each including a gate connected to each of the other stages of the plurality of fuses via the resistors in a 2 to 1 manner for inputting the output signals.