Abstract: A cathode structure of a field emission device includes a gate electrode that is protected by a passivation layer. In one method for manufacturing such a field emission device, an emitter hole is formed through an insulating layer such that the passivation layer overhangs the gate layer, which overhangs an insulating layer. When used in a display system, the gate layer is exposed to an emitter electrode but shielded from an anode.

Abstract: The present invention relates to a method for catalytic dehydrogenation of alkylaromatic hydrocarbons and more particularly, to a method for catalytic dehydrogenation of alkylaromatic hydrocarbons using carbon dioxide as a soft oxidant in the presence of a heterogeneous catalyst comprising both vanadium and iron, which allows operation at a lower reaction temperature due to improve thermodynamic equilibrium and provides an enhanced conversion of hydrocarbons and energy saving.

Abstract: The present invention relates to a non-toxic primer powder composition for small caliber ammunition characterized by comprising potassium nitrate coated with shellac as an oxidizer, and particularly characterized by comprising 25-40 wt % of an initiating explosive, 10-30 wt % of nitrate ester as a fuel, 32-40 wt % of a shellac-coated potassium nitrate (KNO3) as an oxidizer, 5-10 wt % of tetracene as a first sensitizer, 3-9 wt % of a borosilicate powder as a second sensitizer and 0.1-0.2 wt % of a chemical binder.

Abstract: The present invention relates to compositions for weight reduction, comprising a water-soluble low-molecular weight chitosan and a Hibiscus extract, and optionally L-carnitine, and methods of using the composition for weight reduction.

Abstract: Provided is a power up circuit comprising: a reference voltage generator arranged in a semiconductor memory device to generate an internal voltage source of the semiconductor memory device; a first current path control unit that is turned on in accordance with an output of the reference voltage generator to increase a potential of a first node to a voltage of an external voltage source; a second current path control unit that is turned on in accordance with the output of the reference voltage generator to sink the voltage of the first node down to a ground level; and a driving unit for generating a power up signal in accordance with the voltage of the first node.

Abstract: Disclosed is a method for manufacturing a metal-oxide-semiconductor (MOS) device formed in an epitaxial silicon layer on insulator substrate comprising the steps of forming a field oxide layer defined an active region of the MOS device in the silicon layer and forming a gate oxide on the silicon layer; forming a gate electrode on the gate oxide, and self-aligned implanting a dopant of low concentration to form a lightly doped drain region; forming an oxide spacer in both sides of the gate electrode; growing a SiGe epitaxial layer having a lower bandgap than the silicon layer on the portion of the exposed silicon layer; and implanting a dopant of high concentration over the SiGe epitaxial layer to form a highly doped source/drain region. This invention can easily manufacture an SOI MOS device having a low source/drain series resistance and a high breakdown voltage without additional complex processes.

Abstract: An improved method for fabricating a power transistor using an SOI wafer which is capable of using an SOI substrate having a thin Si film, which includes the steps of a first step for forming an SOI layer having a first oxidation film and a single crystal Si thin film by implanting an oxygen ion with respect to a single crystalline substrate and heat-treating the same, a second step for forming source and drain electrodes of a first poly-crystal Si film encircled by a third oxidation film on the SOI substrate, a third step for forming a shallow junction by ion-implanting with respect to the source and drain electrodes of the first poly-crystalline Si film, a fourth step for forming a second poly-crystalline Si film by a reactive ion etching method with respect to the third oxide film so as to form a gate electrode, and a fifth step for stabilizing a voltage at a lower channel portion, which voltage is supplied thereto through a p-type region of the SOI layer, and for ion-implanting a p-type dopant ion using a