Patents by Inventor Jong-Soo Park

Jong-Soo Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170185403
    Abstract: A processor includes a front end to receive an instruction, a decoder to decode the instruction, a set operations logic unit (SOLU) to execute the instruction, and a retirement unit to retire the instruction. The SOLU includes logic to store a first set of key-value pairs in a content-associative data structure, to receive a second set of key-value pairs, and to identify key-value pairs in the two sets with matching keys. The SOLU includes logic to add the second set of key-value pairs to the first set to produce an output set, and to apply an operation to the values of key-value pairs with matching keys, generating a single value for the matching key. The SOLU includes logic to produce an output set that includes key-value pairs from the first set with matching keys, and to discard key-value pairs from the first set with unique keys.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 29, 2017
    Inventors: Michael J. Anderson, Sheng R. Li, Jong Soo Park, Md Mostofa Ali Patwary, Nadathur Rajagopalan Satish, Mikhail Smelyanskiy, Narayanan Sundaram
  • Publication number: 20170177361
    Abstract: An apparatus and method are described for accelerating graph analytics. For example, one embodiment of a processor comprises: an instruction fetch unit to fetch program code including set intersection and set union operations; a graph accelerator unit (GAU) to execute at least a first portion of the program code related to the set intersection and set union operations and generate results; and an execution unit to execute at least a second portion of the program code using the results provided from the GAU.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventors: Michael Anderson, Sheng Li, Jong Soo Park, MD Mostafa Ali Patwary, Nadathur Rajagopalan Satish, Mikhail Smelyanskiy, Narayanan Sundaram
  • Publication number: 20170168827
    Abstract: A processing device includes a sorting module, which adds to each of a plurality of elements a position value of a corresponding position in a register rest resulting in a plurality of transformed elements in corresponding positions. The plurality of elements include a plurality of bits. The sorting module compares each of the plurality of transformed elements to itself and to one another. The sorting module also assigns one of an enabled or disabled indicator to each of the plurality of the transformed elements based on the comparison. The sorting module further counts a number of the enabled indicators assigned to each of the plurality of the transformed elements to generate a sorted sequence of the plurality of elements.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: Asit K. Mishra, Deborah T. Marr, Jong Soo Park, Nadathur Rajagopalan Satish, Mikhail Smelyanskiy, Michael Anderson, Mostofa Ali Patwary, Narayanan Sundaram, Sheng Li
  • Publication number: 20170154062
    Abstract: Disclosed herein is a data evaluation device using similarity for searching a plurality of documents for a document similar or substantially identical to a given document, a method therefor, and a computer-readable recording medium with the method recorded thereon. The data evaluation device using similarity includes an input unit receiving first and second records, a record set generating unit arraying the first and second records in alphabetical order and giving one token to each arrayed word to generate corresponding first and second record sets, and a similarity verifying unit determining that the first and second records are not similar when a position at which a comparison token in the first record set, which is allocated to a word identical to a median value token disposed at a position corresponding to a median value in the second record set, is in a preset range.
    Type: Application
    Filed: December 23, 2015
    Publication date: June 1, 2017
    Applicant: SUNGSHIN WOMEN'S UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventor: Jong Soo PARK
  • Patent number: 9656782
    Abstract: A container structure is provided for detachable coupling of containers. The detachable coupling structure of a first container includes a top portion with an upstanding perimeter having radial protrusions extending from a surface of the upstanding perimeter, and a container bottom portion having a complementary structure to engage the radial protrusions of the top portion of a second container for the purpose of detachably coupling two or more containers end to end. In one embodiment, two containers placed end to end with their respective structures aligned to be engaged are rotated in opposite directions to fully engage the protrusions of one container with the complementary structure of the other. A rim around the top portion of a container in a second embodiment has a larger diameter than the top portion. The rim may be pushed through a flexible opening into a recess in the bottom of another container.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: May 23, 2017
    Inventor: Jong Soo Park
  • Publication number: 20170129047
    Abstract: The present invention relates to a thin plate bonding method or a thin plate assembly, and more particularly, to a thin plate bonding method which includes coating with a coating material after increasing a surface roughness or increasing a surface roughness through coating with a coating material, and then, conducting diffusion bonding, such that excellent bonding strength is achieved even when the diffusion bonding is performed at low temperature and low pressure, thin plate deformation by thermal stress may be prevented, and high air tightness may be obtained since the coating material fills micro-pores.
    Type: Application
    Filed: June 17, 2015
    Publication date: May 11, 2017
    Applicant: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Jong-Soo PARK, Kyung-Ran HWANG, Dong-Wook LEE, Ju-Seok PARK, Chun-Boo LEE, Sung-Wook LEE, Duck-Kyu OH, Jin-Woo PARK, Min-Ho JIN
  • Patent number: 9645930
    Abstract: Technologies for dynamic home tile mapping are described. an address request can be received from a processing core, the processing core being associated with a home tile table, the home tile table including respective mappings of one or more directory addresses to one or more home tiles. A buffer can be scanned to identify a presence of the address within the buffer. Based on an identification of the presence of the address within the buffer, a home tile identifier corresponding to the address can be provided from the buffer.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 9, 2017
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Daehyun Kim, Jong Soo Park, Richard M. Yoo
  • Patent number: 9616379
    Abstract: The present invention relates to a method for preparing a hydrogen separation membrane capable of preventing the plating of Pd inside a porous support and a porous shielding layer when a separation membrane is prepared; a hydrogen separation membrane prepared therefrom; and a use thereof. In addition, the present invention relates to a device for preparing a hydrogen separation membrane; and a method for preparing a hydrogen separation membrane using the device, and in particular, relates to a device for preparing a hydrogen separation membrane capable of stably growing a Pd-containing separation membrane for hydrogen gas separation as a plating solution grows from the upper surface of a porous support to a uniform thickness by simply shielding the lower surface of the porous support when a hydrogen separation membrane is prepared using an electroless plating method.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: April 11, 2017
    Assignee: Korea Institute of Energy Research
    Inventors: Shin Kun Ryi, Beom Seok Seo, Jong Soo Park, Dong Wook Lee, Sung Wook Lee
  • Publication number: 20170090921
    Abstract: A processor includes a decode unit to decode an instruction indicating a source packed data operand having source data elements and indicating a destination storage location. Each of the source data elements has a source data element value and a source data element position. An execution unit, in response to the instruction, stores a result packed data operand having result data elements each having a result data element value and a result data element position. Each result data element value is one of: (1) equal to a source data element position of a source data element, closest to one end of the source operand, having a source data element value equal to the result data element position of the result data element; and (2) a replacement value, when no source data element has a source data element value equal to the result data element position of the result data element.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Applicant: INTEL CORPORATION
    Inventors: Christopher J. Hughes, Jong Soo Park
  • Patent number: 9587541
    Abstract: The present invention relates to a configuration method of a multifunctional particulate filter (MFPF), capable of reducing the content of particulate material (PM), carbon monoxide (CO) and hydrocarbons (HC), and increasing the content of nitrogen dioxide (NO2). The MFPF may coat zeolite and an oxidation catalyst on both exhaust gas intake/discharge sides simultaneously, so as to minimize the slippage of HC and generate high-concentration NO2.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 7, 2017
    Assignee: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Jong-Soo Park, Young-Jae Lee, Kyung-Ran Hwang, Shin-Kun Ryi, Dong-Kook Kim, Tae-Hwan Kim, Chun-Boo Lee, Kyung-Sun Yoo
  • Patent number: 9563425
    Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: February 7, 2017
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Changkyu Kim, Daehyun Kim, Victor W. Lee, Jong Soo Park
  • Publication number: 20160378442
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to optimize sparse matrix execution. An example disclosed apparatus includes a context former to identify a matrix function call from a matrix function library, the matrix function call associated with a sparse matrix, a pattern matcher to identify an operational pattern associated with the matrix function call, and a code generator to associate a function data structure with the matrix function call exhibiting the operational pattern, the function data structure stored external to the matrix function library, and facilitate a runtime link between the function data structure and the matrix function call.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Hongbo Rong, Jong Soo Park, Mikhail Smelyanskiy, Geoff Lowney
  • Publication number: 20160378651
    Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Inventors: Subramanya R. Dulloor, Rajesh M. Sankaran, David A. Koufaty, Christopher J. Hughes, Jong Soo Park, Sheng Li
  • Patent number: 9452932
    Abstract: The present invention relates to a hydrogen production module by an integrated reaction/separation process, and a hydrogen production reactor using the same, and more specifically, provides a hydrogen production apparatus which laminates a plurality of layered unit cells, is mounted in a pressure-resistant chamber, and can be operated at a high pressure, wherein the unit cell comprises a first modified catalyst, and a second modified catalyst opposite to a hydrogen separator. The hydrogen production module can produce hydrogen using a hydrocarbon, carbon monoxide and an alcohol as sources. Particularly, all the modified catalysts are formed into a porous metal plate form, thereby maximizing the heat transfer effect necessary for reaction.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: September 27, 2016
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jong-Soo Park, Kyung-Ran Hwang, Shin-Kun Ryi, Chun-Boo Lee, Sung-Wook Lee, Jin-Woo Park
  • Patent number: 9427700
    Abstract: The present invention relates to a multilayer module for hydrogen separation using a pressure-resistant chamber so that unit cells using a metal separation membrane through which only hydrogen selectively passes are stacked to improve separation efficiency, and a mixed gas is uniformly supplied into each of the unit cells. In the multilayer module, the unit cells are stacked on each other, and the mixed gas is supplied into the chamber. Also, mixed gas input ports are each disposed in the side surfaces of the unit cells to supply the mixed gas.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: August 30, 2016
    Assignee: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Jong-Soo Park, Kyung-Ran Hwang, Shin-Kun Ryi, Chun-Boo Lee, Sung-Wook Lee, Jin-Woo Park
  • Patent number: 9415343
    Abstract: The present invention relates to a hydrogen separation membrane which coats granular ceramic onto the surface of a porous metal support and which coats a hydrogen permeation metal thereon so as to inhibit diffusion between the support and a hydrogen separation layer, and to a method for manufacturing same. As a result, the metal support can be modularized with ease, the hydrogen permeation layer can be made thinner to increase the amount of hydrogen permeation, the use of a separation material can be minimized, and the hydrogen separation membrane can have higher competitiveness.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: August 16, 2016
    Assignee: Korea Institute of Energy Research
    Inventors: Jong-Soo Park, Kyung-Ran Hwang, Shin-Kun Ryi, Tae-Hwan Kim, Chun-Boo Lee, Sung-Wook Lee
  • Publication number: 20160188474
    Abstract: Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.
    Type: Application
    Filed: December 26, 2014
    Publication date: June 30, 2016
    Applicant: Intel Corporation
    Inventors: Ren Wang, Andrew J. Herdrich, Yen-cheng Liu, Herbert H. Hum, Jong Soo Park, Christopher J. Hughes, Namakkal N. Venkatesan, Adrian C. Moga, Aamer Jaleel, Zeshan A. Chishti, Mesut A. Ergin, Jr-shian Tsai, Alexander W. Min, Tsung-yuan C. Tai, Christian Maciocco, Rajesh Sankaran
  • Publication number: 20160179544
    Abstract: A processor includes a core, a hardware prefetcher, and a prefetcher control module. The hardware prefetcher includes logic to make speculative prefetch requests, through a memory subsystem, for elements for execution by the core, and logic to store prefetched elements in a cache. The prefetcher control module includes logic to selectively suppress, based on a hardware-prefetch suppression instruction executed by the core, a speculative prefetch request to be made by the hardware prefetcher.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Inventors: Alexander F. Heinecke, Christopher J. Hughes, Daehyun Kim, Jong Soo Park
  • Patent number: 9333477
    Abstract: Disclosed is a hydrocarbon reforming device using a micro channel heater capable of utilizing combustion heat of a fuel as an energy source for reforming reaction of hydrocarbon, which includes metal sheets having micro channels laminated in plural, thus being suitably used as a middle and small compact type device for hydrogen production. Specifically, in the case where a hydrogen purification process is applied to a hydrogen production device combined with a separation membrane, since the hydrogen-containing gas, which does not penetrate the separation membrane, can be utilized as a fuel, the inventive device may be utilized as a hydrogen production system having high efficiency.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: May 10, 2016
    Assignee: Korea Institute of Energy Research
    Inventors: Jong-Soo Park, Kyung-Ran Hwang, Chun-Boo Lee, Sung-Wook Lee, Shin-Kun Ryi
  • Patent number: 9323525
    Abstract: In an embodiment, a processor includes a vector execution unit having a plurality of lanes to execute operations on vector operands, a performance monitor coupled to the vector execution unit to maintain information regarding an activity level of the lanes, and a control logic coupled to the performance monitor to control power consumption of the vector execution unit based at least in part on the activity level of at least some of the lanes. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: April 26, 2016
    Assignee: Intel Corporation
    Inventors: Daehyun Kim, Jong Soo Park, Dong Hyuk Woo, Richard M. Yoo, Christopher J. Hughes