Abstract: In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively.

Abstract: A distributed translator and an operation method of the distributed translator are proposed. The distributed translator includes: a demodulator demodulating a received signal to extract a transport stream and synchronization information from the received signal; a modulator generating an output frame based on the synchronization information to modulate the output frame; and a transmitter transmitting the modulated output frame according to a transmission timing.

Abstract: A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.

Abstract: Provided are an apparatus and method for allocating resources in a mobile communication system. The apparatus includes a modulating/coding unit for modulating transmission data of one or more users according to a predetermined modulation scheme and for outputting a complex signal; a 2-Dimensional (2D)/1-Dimensional (1D) converter for converting the complex signal into a 1D signal; and a re-modulator for reconstructing the 1D signal to a 2D signal and for allocating two components of the 2D signal to two different frequency bands.

Abstract: A phase-change random access memory (PRAM) device includes a plurality of banks, a plurality of column redundancy cell arrays, and a plurality of column redundancy write drivers. Each of the plurality of column redundancy cell arrays corresponds to at least one of the banks. Each of the plurality of column redundancy write drivers corresponds to at least one of the column redundancy cell arrays. The column redundancy write drivers are configured to transmit respective redundancy test data to the corresponding ones of the column redundancy cell arrays in response to a test control signal, which may be activated in response to each program pulse for writing data. Related test and access methods are also discussed.

Abstract: An apparatus and method for determining a pilot pattern in a Broadband Wireless Access (BWA) communication system are provided. In the pilot pattern determining method, an Orthogonal Frequency Division Multiplexing (OFDM) demodulator generates frequency-domain data by fast-Fourier-transform (FFT)-processing a received signal. A pilot pattern decider calculates a coherence bandwidth and a coherence time using subcarrier values received from the OFDM demodulator, and selects one of a plurality of pilot patterns according to the ratio of the coherence bandwidth to the coherence time.

Abstract: A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.

Abstract: A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit line with each of the plurality of local bit lines. Each column select transistor has a resistance that depends on distance from the write circuit and the read circuit.

Abstract: Provided are a receiver and a method for detecting a signal in a multiple antenna system. The receiver includes a filter coefficient calculator and a signal detector. After separating a first signal portion and a second signal portion, the filter coefficient calculator calculates an MMSE filter coefficient using a Matrix Inversion Lemma such that an inverse matrix of the first signal portion has a predetermined constant value regardless of a repetition signal detection process. The signal detector detects a relevant transmission signal from an interference-removed reception signal using the MMSE filter coefficient.

Abstract: A variable resistance memory device includes a memory cell array having a plurality of memory cells, a write driver which supplies a step-down set current to the memory cells, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver. The set program control circuit controls the duration of the step-down set current in accordance with at least one of data contained in an mode register set (MRS) and a conductive state of a fuse element.

Abstract: A phase-change random access memory (PRAM) device includes a plurality of banks, a plurality of column redundancy cell arrays, and a plurality of column redundancy write drivers. Each of the plurality of column redundancy cell arrays corresponds to at least one of the banks. Each of the plurality of column redundancy write drivers corresponds to at least one of the column redundancy cell arrays. The column redundancy write drivers are configured to transmit respective redundancy test data to the corresponding ones of the column redundancy cell arrays in response to a test control signal, which may be activated in response to each program pulse for writing data. Related test and access methods are also discussed.

Abstract: In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively.

Abstract: A distributed translator and an operation method of the distributed translator are proposed. The distributed translator includes: a demodulator demodulating a received signal to extract a transport stream and synchronization information from the received signal; a modulator generating an output frame based on the synchronization information to modulate the output frame; and a transmitter transmitting the modulated output frame according to a transmission timing.

Abstract: In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively.

Abstract: A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

Abstract: A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.

Abstract: Provided are an apparatus and method for allocating resources in a mobile communication system. The apparatus includes a modulating/coding unit for modulating transmission data of one or more users according to a predetermined modulation scheme and for outputting a complex signal; a 2-Dimensional (2D)/1-Dimensional (1D) converter for converting the complex signal into a 1D signal; and a re-modulator for reconstructing the 1D signal to a 2D signal and for allocating two components of the 2D signal to two different frequency bands.

Abstract: A variable resistance memory device includes a memory cell array having a plurality of memory cells, a write driver which supplies a step-down set current to the memory cells, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.

Abstract: A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.

Abstract: An apparatus and method for determining a pilot pattern in a Broadband Wireless Access (BWA) communication system are provided. In the pilot pattern determining method, an Orthogonal Frequency Division Multiplexing (OFDM) demodulator generates frequency-domain data by fast-Fourier-transform (FFT)-processing a received signal. A pilot pattern decider calculates a coherence bandwidth and a coherence time using subcarrier values received from the OFDM demodulator, and selects one of a plurality of pilot patterns according to the ratio of the coherence bandwidth to the coherence time.