Abstract: A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

Abstract: A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.

Abstract: A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit line with each of the plurality of local bit lines. Each column select transistor has a resistance that depends on distance from the write circuit and the read circuit.

Abstract: A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.

Abstract: A channel equalizer and a method of equalizing a channel.

Abstract: A test element group structure having 3-dimensional SRAM cell transistors includes a bulk metal-oxide-semiconductor (MOS) transistor formed at a semiconductor substrate and a first interlayer insulating layer covering the bulk MOS transistor. A lower thin film transistor is disposed on the first interlayer insulating layer, and the lower thin film transistor is covered with a second interlayer insulating layer. An upper thin film transistor is disposed on the second interlayer insulating layer, and the upper thin film transistor is covered with a third interlayer insulating layer. A metal node plug is disposed to pass through the first to third interlayer insulating layers. The metal node plug electrically connects a first impurity region of the bulk MOS transistor, a first impurity region of the lower thin film transistor, and a first impurity region of the upper thin film transistor with each other.

Abstract: In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively.

Abstract: Provided is a content addressable memory (CAM) cell for operating at a high speed. The CAM cell includes a bit line pair consisting of a bit line and an inverted bit line, first and second memory cells, a match line, and first and second comparators. The first memory cell includes a first storage unit for storing data and first connectors for connecting the bit line pair to the first storage unit and for transmitting data input through the bit line pair to the first storage unit. The second memory cell includes a second storage unit for storing data and second connectors for connecting the bit line pair to the second storage unit and for transmitting the data input through the bit line pair to the second storage unit. The first comparator is connected to the match line and the first storage unit and connects the match line to a first voltage or disconnects the match line from the first voltage in response to search data input through a search line and the data stored in the first storage unit.

Abstract: A synchronization method in an OFDM based communication system. A transmitting side generates and transmits an OFDM symbol having a constant cyclic prefix, independent of time domain data symbols that are to be transmitted. A receiving side estimates a timing synchronization error based on the known cyclic prefix. Because the timing synchronization error is estimated based on the constant cyclic prefix, which is always known, a highly reliable correlation is achieved, thereby improving the accuracy of synchronization.

Abstract: A circuit for detecting the recording/playback mode of a system, e.g., a video tape recorder (VTR), for recording/playing back an image signal on/from a recording medium, using first and second input signals derived from pilot signals also recorded on the recording medium. The circuit includes a first peak value detector for detecting the peak value of the first input signal, and for generating a first output signal representative of the peak value of the first input signal, and a second peak value detector for detecting the peak value of the second input signal, and for generating a second output signal representative of the peak value of the second input signal.