Patents by Inventor Jong Tae Moon

Jong Tae Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230311250
    Abstract: Proposed are a copper sintering paste composition and a method of preparing the same. The copper sintering paste composition can replace conventional bonding material such as solder and lead-free solder and has excellent heat resistance, heat-generating properties, thermal conductivity, and bonding strength.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 5, 2023
    Applicant: Hojeonable Inc.
    Inventors: Jong Tae Moon, Kwang Mo Jung
  • Publication number: 20230131422
    Abstract: Proposed is an epoxy flux film that is to be positioned between a semiconductor substrate and a device and is heated and pressed without addition of an additional flux. Thus, device-substrate soldering and sealing are simultaneously performed, and interference of light reflected from the solder can be reduced.
    Type: Application
    Filed: October 21, 2022
    Publication date: April 27, 2023
    Applicant: Hojeonable Inc.
    Inventors: Jong Tae MOON, Kwang Mo JUNG
  • Patent number: 9980393
    Abstract: A pattern-forming method for forming a conductive circuit pattern, the pattern-forming method including the steps of: preparing a pattern-forming composition composed of: Cu powder; solder particles for electrically coupling the Cu powder; a polymer resin; a deforming agent that is selected from among acrylate oligomer, polyglycols, glycerides, polypropylene glycol, dimethyl silicon, simethinecone, tributyl phosphare, and polymethylsiloxane, and that increases bonding force between the Cu powder and the solder particles; a curing agent; and a reductant; forming a circuit pattern by printing the pattern-forming composition on a substrate; heating the circuit pattern at a temperature effective to cure the pattern-forming composition and provide the conductive circuit pattern; and electrolytically plating a metal layer onto the conductive circuit pattern. A circuit pattern having superior conductivity is formed at low cost.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: May 22, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung Eom, Kwang-Seong Choi, Hyun-cheol Bae, Jung Hyun Noh, Jong Tae Moon
  • Patent number: 9462736
    Abstract: Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: October 4, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung Eom, Jong Tae Moon, Sangwon Oh, Keonsoo Jang
  • Patent number: 9293689
    Abstract: A piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: March 22, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Chi Hoon Jun, Sang Choon Ko, Jong Tae Moon
  • Patent number: 9155236
    Abstract: Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: October 6, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung Eom, Jong Tae Moon, Sangwon Oh, Keonsoo Jang
  • Publication number: 20150237739
    Abstract: The present invention relates to a pattern-forming composition used to form a conductive circuit pattern. The pattern-forming composition comprises Cu powders, a solder for electrically coupling the Cu powders, a polymer resin, a curing agent and a reductant. According to the present invention, a circuit pattern having superior conductivity can be formed at low cost.
    Type: Application
    Filed: May 5, 2015
    Publication date: August 20, 2015
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung EOM, Kwang-Seong CHOI, Hyun-cheol BAE, Jung Hyun NOH, Jong Tae MOON
  • Publication number: 20140317918
    Abstract: Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yong Sung EOM, Jong Tae MOON, Sangwon OH, Keonsoo JANG
  • Publication number: 20140317915
    Abstract: Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.
    Type: Application
    Filed: July 8, 2014
    Publication date: October 30, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Yong Sung EOM, Jong Tae MOON, Sangwon OH, Keonsoo JANG
  • Publication number: 20140318615
    Abstract: A conductive composition for a front electrode busbar of a silicon solar cell includes a metallic powder, a solder powder, a curable resin, a reducing agent, and a curing agent. A method of manufacturing a front electrode busbar of a silicon solar cell includes applying the composition to the front surface of the silicon solar cell wherein its front electrode finger line is formed. A substrate includes a front electrode busbar of a silicon solar cell, formed with a conductive composition. A silicon solar cell includes one or more electrodes containing a conductive composition including a conductive powder, a curable resin, a reducing agent, and a curing agent. A method of manufacturing the silicon solar cell includes forming a first electrode array with a first conductive composition, forming a second electrode, and forming a third electrode with a third conductive composition.
    Type: Application
    Filed: July 7, 2014
    Publication date: October 30, 2014
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Soo Young OH, Yong Sung EOM, Jong Tae MOON, Kwang Seong CHOI
  • Patent number: 8802760
    Abstract: Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 12, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Sung Eom, Jong Tae Moon, Sangwon Oh, Keonsoo Jang
  • Patent number: 8723292
    Abstract: Disclosed is a silicon interposer that can reduce the entire area of a semiconductor package and increase the degree of integration by forming inductors at a lower part in addition to an upper part of a silicon substrate. The silicon interposer includes a silicon substrate, an upper inductor layer formed at the upper part of the silicon substrate and a lower inductor layer formed at the lower part of the silicon substrate.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: May 13, 2014
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hyun-Cheol Bae, Kwang-Seong Choi, Jong Tae Moon, Jong-Moon Park
  • Publication number: 20140054262
    Abstract: Disclosed is a piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode.
    Type: Application
    Filed: October 29, 2013
    Publication date: February 27, 2014
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Chi Hoon JUN, Sang Choon KO, Jong Tae MOON
  • Patent number: 8598768
    Abstract: Disclosed is a piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: December 3, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chi Hoon Jun, Sang Choon Ko, Jong Tae Moon
  • Patent number: 8524571
    Abstract: Disclosed is a vacuum wafer level packaging method for a micro electro mechanical system device, including: forming a plurality of via holes on an upper wafer for protecting a micro electro mechanical system (MEMS) wafer; forming at least one metal layer on inner walls of the plurality of via holes and regions extended from the plurality of via holes; arranging and bonding the upper wafer and the MEMS wafer at atmospheric pressure; applying solder paste to the regions extended from the plurality of via holes; filling a solder in the plurality of via holes by increasing the temperature of a high-vacuum chamber to melt the solder paste; and changing the solder in the plurality of via holes to a solid state by lowering the temperature of the high-vacuum chamber.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 3, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong Tae Moon, Yong Sung Eom, Hyun-Cheol Bae
  • Publication number: 20130146342
    Abstract: The present invention relates to a pattern-forming composition used to form a conductive circuit pattern. The pattern-forming composition comprises Cu powders, a solder for electrically coupling the Cu powders, a polymer resin, a curing agent and a reductant. According to the present invention, a circuit pattern having superior conductivity can be formed at low cost.
    Type: Application
    Filed: September 12, 2012
    Publication date: June 13, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Yong Sung EOM, Kwang-Seong Choi, Hyun-cheol Bae, Jung Hyun Noh, Jong Tae Moon
  • Patent number: 8420722
    Abstract: Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: April 16, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Yong Sung Eom, Jong Tae Moon, Sangwon Oh, Keonsoo Jang
  • Publication number: 20130087884
    Abstract: Disclosed is a silicon interposer that can reduce the entire area of a semiconductor package and increase the degree of integration by forming inductors at a lower part in addition to an upper part of a silicon substrate. The silicon interposer includes a silicon substrate, an upper inductor layer formed at the upper part of the silicon substrate and a lower inductor layer formed at the lower part of the silicon substrate.
    Type: Application
    Filed: June 11, 2012
    Publication date: April 11, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hyun-Cheol BAE, Kwang-Seong CHOI, Jong Tae Moon, Jong-Moon PARK
  • Publication number: 20130074918
    Abstract: Disclosed are vacuum window glazing including a solar cell function and a manufacturing method thereof. The vacuum window glazing includes a first sheet glass, a second sheet glass that is vacuum-bonded to the first sheet glass; a vacuum layer that is formed between the first sheet glass and the second sheet glass; and a solar cell panel that is formed on a surface of the second sheet glass in a direction of the vacuum layer. By this configuration, power can be produced through the solar cell formed within the vacuum window glazing while more increasing the heat insulation effect of the vacuum window glazing, and the cooling and heating efficiency of the building can be greatly improved using the outer wall covered with glass.
    Type: Application
    Filed: July 30, 2012
    Publication date: March 28, 2013
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jin Woo Jeong, Yoon Ho Song, Sung Youl Choi, Je Ha Kim, Jong Tae Moon, Jung Wook Lim, Hun Kyun Pak
  • Publication number: 20120288983
    Abstract: Disclosed is a method for manufacturing a dye sensitized solar cell module. The method includes putting at least one or more heating-wires on an upper portion of an electrode of each solar cell sub-module; applying a metal paste on the upper portion of the electrode including at least one or more heating-wires; and heating and curing the metal paste by after overlapping the electrodes of a plurality of solar cell sub-modules each other, allowing a current to flow to at least one or more heating-wires.
    Type: Application
    Filed: April 30, 2012
    Publication date: November 15, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Moo Jung Chu, Ju Mi Kim, Yong Sung Eom, Ah Ram Jeon, Jong Tae Moon