Abstract: In a method of manufacturing a semiconductor device, a string structure including a selection transistor and a memory cell on a substrate. An insulation layer pattern is formed on the substrate to cover the string structure. The insulation layer pattern includes at least one opening exposing a portion of the substrate adjacent to the selection transistor. A seed layer including a single-crystalline material is formed in the opening. An amorphous thin film including an amorphous material is formed on the insulation layer pattern and the seed layer. The amorphous thin film is transformed into a single-crystalline thin film, using the single-crystalline material in the seed layer as a seed during a phase transition of the amorphous thin film, to form a channel layer on the insulation layer pattern and the seed layer. Therefore, the semiconductor device including the channel layer having the single-crystalline thin film may be manufactured.

Abstract: A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

Abstract: A wafer temporary bonding method using silicon direct bonding (SDB) may include preparing a carrier wafer and a device wafer, adjusting roughness of a surface of the carrier wafer, and combining the carrier wafer and the device wafer using the SDB. Because the method uses SDB, instead of an adhesive layer, for a temporary bonding process, a module or process to generate and remove an adhesive is unnecessary. Also, a defect in a subsequent process, for example, a back-grinding process, due to irregularity of the adhesive may be prevented.

Abstract: In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

Abstract: In a conductive structure, method of forming the conductive structure, a vertical-type pillar transistor and a method of manufacturing the vertical-type pillar transistor, the conductive structure includes a pillar provided on a substrate. A first conductive layer pattern is provided on a sidewall of the pillar, at least a portion of the first conductive layer pattern facing the sidewall of the pillar. A second conductive layer pattern is provided on a surface of the first conductive layer pattern, the second conductive layer pattern facing the sidewall of the pillar. A hard mask pattern covers upper surfaces of the first conductive layer pattern and the pillar. The conductive structure includes an electric conductor with a relatively low resistance. The conductive structure may be used as an electrode of a memory device.

Abstract: In a fin field effect transistor (FET), an active pattern protrudes in a vertical direction from a substrate and extends across the substrate in a first horizontal direction. A first silicon nitride pattern is formed on the active pattern, and a first oxide pattern and a second silicon nitride pattern are sequentially formed on the substrate and on a sidewall of a lower portion of the active pattern. A device isolation layer is formed on the second silicon nitride pattern, and a top surface of the device isolation layer is coplanar with top surfaces of the oxide pattern and the second silicon nitride pattern. A buffer pattern having an etching selectivity with respect to the second silicon nitride pattern is formed between the first oxide pattern and the second silicon nitride pattern.

Abstract: In a vertical-type non-volatile memory device, first and second single-crystalline semiconductor pillars are arranged to face each other on a substrate. Each of the first and second single-crystalline semiconductor pillars has a rectangular parallelepiped shape with first, second, third and fourth sidewalls. A first tunnel oxide layer, a first charge storage layer and a first blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the first single-crystalline semiconductor pillar. A second tunnel oxide layer, a second charge storage layer and a second blocking dielectric layer are sequentially stacked on the entire surface of the first sidewall of the second single-crystalline semiconductor pillar. A word line makes contact with surfaces of both the first and second blocking dielectric layers. The word line is used in common for the first and second single-crystalline semiconductor pillars.

Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties.

Abstract: A semiconductor device includes (a) a semiconductor layer formed on an electrically insulating layer, (b) a gate insulating film formed on the semiconductor layer, (c) a gate electrode formed on the gate insulating film, and (d) a field insulating film formed on the semiconductor layer for defining a region in which a semiconductor device is to be fabricated. The semiconductor layer includes (a1) source and drain regions formed in the semiconductor layer around the gate electrode, the source and drain regions containing first electrically conductive type impurity, (a2) a body contact region formed in the semiconductor layer, the body contact region containing second electrically conductive type impurity, and (a3) a carrier path region formed in the semiconductor layer such that the carrier path region does not make contact with the source and drain regions, but makes contact with the body contact region, the carrier path region containing second electrically conductive type impurity.

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

Abstract: Methods of fabricating SOI wafers are provided including providing a donor wafer and forming a hydrogen ion implantation layer in the donor wafer. A circumference portion of one side of the donor wafer is recessed to form a height difference. The one side of the donor wafer and a handle wafer are bonded to form a bonded wafer. The bonded wafer is heat treated to separate the bonded wafer along the hydrogen ion implantation layer.

Abstract: In a method of forming a single crystalline semiconductor layer, an amorphous layer may be formed on a seed layer that includes a single crystalline material. The single crystalline layer may be formed from the amorphous layer by irradiating a laser beam onto the amorphous layer using the seed layer as a seed for a phase change of the amorphous layer. The laser beam may have an energy for melting the amorphous layer, and the laser beam may be irradiated onto the amorphous layer without generating a superimposedly irradiated region of the amorphous layer. The single crystalline layer may include a high density of large-sized grains without generating a protrusion thereon through a simple process so that a semiconductor device including the single crystalline layer may have a high degree of integration and improved electrical characteristics.

Abstract: A method of fabricating a semiconductor device includes forming an insulation layer structure on a single-crystalline silicon substrate, forming a first insulation layer structure pattern comprising a first opening by etching a portion of the insulation layer structure, filling the first opening with a non-single-crystalline silicon layer, and forming a single-crystalline silicon pattern by irradiating a first laser beam onto the non-single-crystalline silicon layer. The method also includes forming a second insulation layer structure pattern comprising a second opening by etching a portion of the first insulation layer structure, filling the second opening with a non-single-crystalline silicon-germanium layer, and forming a single-crystalline silicon-germanium pattern by irradiating a second laser beam onto the non-single-crystalline silicon-germanium layer.

Abstract: Disclosed is a fin transistor and a planar transistor and a method of forming the same. The fin transistor and the planar transistor are formed to have gate electrodes with similar thicknesses by selectively recessing a semiconductor substrate in a planar region where the planar transistor is formed.

Abstract: Phosphor paste compositions, phosphor layers and electron emitting devices are provided. The phosphor paste composition includes a phosphor, a binder including a photocurable monomer and an acrylic resin with an acid value ranging from about 150 mgKOH/g to about 200 mgKOH/g, a photoinitiator, and a solvent. The phosphor layer is obtained from the phosphor paste composition, and the electron emission device includes the phosphor layer. The phosphor paste compositions provide superior phosphor layer pattern resolution, plasticity, printability, and storage stability.

Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.

Abstract: A method of forming a thin layer including providing a first single-crystalline silicon layer partially exposed through an opening in an insulation pattern and forming an epitaxial layer on the first single-crystalline silicon layer and forming an amorphous silicon layer on the insulation pattern, the amorphous silicon layer having a first portion adjacent the epitaxial layer and a second portion spaced apart from the first portion, wherein the amorphous silicon layer is formed on the insulation pattern at substantially the same rate at the first portion and at a second portion. The amorphous silicon layer may be formed to a uniform thickness without a thinning defect.

Abstract: In a semiconductor device and a method of manufacturing the same, a conductive structure is formed on an active region defined by a device isolation layer on a semiconductor substrate. The conductive structure includes a gate pattern and source/drain regions adjacent to the gate pattern. A first semiconductor layer is formed on the active region by a selective epitaxial growth (SEG) process. An amorphous layer is formed on the first semiconductor layer. A second semiconductor layer is formed from a portion of the amorphous layer by a solid-phase epitaxy (SPE) process. Elevated structures are formed on the source/drain regions by removing a remaining portion of the amorphous layer from the substrate so the elevated structure includes the first semiconductor layer and the second semiconductor layer stacked on the first semiconductor layer. The device isolation layer may be prevented from being covered with the elevated structures, to thereby prevent contact failures.

Abstract: In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively formed into a first device isolation pattern on the first area. The first insulation layer is removed from the second area of the substrate and a semiconductor layer is formed on the second area of the substrate by a SEG process. The semiconductor layer on the second area is patterned into a second active pattern including a recessed portion and a second insulation pattern in the recessed portion is formed into a second device isolation pattern on the second area. Accordingly, grain defects in the LEG process and lattice defects in the SEG process are mitigated or eliminated.