Abstract: Disclosed is a method for preparation of a chitosan oligosaccharide composition capable of increasing a content of disaccharide in chitosan oligosaccharide with excellent effects of reducing HbAlc and blood glucose as well as excellent thermal stability. The method for preparation of a chitosan oligosaccharide composition includes: adding chitosan to distilled water to swell the chitosan; firstly treating the chitosan with a chitosanase to prevent the chitosan solution from becoming a state of being viscose, then, adding an organic acid to a mixed solution of the chitosan and chitosanase at a predetermined time interval bit by bit over several additions; allowing mutual reaction between the chitosan, chitosanase and organic acid; and inactivating the chitosanase to obtain the chitosan oligosaccharide composition. Further, a medicine and/or health supplement food which is effective in preventing and treating diabetes, including at least 40% of disaccharide without monosaccharide, is also disclosed.

Abstract: A wiper blade apparatus, having a main lever which is formed of synthetic resin, includes a rotation shaft that is disposed at a center of the main lever, and formed to connect both sidewalls of the main lever; and a connector that is rotatably coupled to a rotation shaft, and formed to be detachable from the rotation shaft, wherein a first fool-proof assembly unit is formed at the rotation shaft, and restricts a range of a rotation angle of the connector that prevents misassembly of the connector; and a second fool-proof assembly unit is formed on the coupling unit of the connector and, in correspondence with the first fool-proof assembly unit, restricts a range of a rotation angle of the connector.

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract: Provided is a bumper beam assembly system. The A bumper beam assembly system includes a bumper beam and a stay connecting the bumper beam to a vehicle, wherein the stay is replaceably coupled to both sides of the bumper beam to occupy a corner portion of the bumper beam.

Abstract: The present invention relates to a novel use of herbal extracts in a pharmaceutical composition for prevention and treatment of nephritis and, more particularly, to a pharmaceutical composition and a health functional food for prevention and/or treatment of nephritis that contains at least one herbal extract selected from the group consisting of a Crataegi Fructus extract, a Cinnamomi Cortex extract, a Prunella Spica extract, and an Equiseti Herba extract, a method for prevention and/or treatment of nephritis using the herbal extract, and a use of the herbal extract in preparation of a composition for prevention and/or treatment of nephritis. The herbal extract has a good therapeutic effect for nephritis on a nephritis model of which the nephritis is induced by a drug such as gentamicin, cisplatin, etc., and a good inhibitory activity on the growth of mesangial cells in kidneys, thereby providing a very useful means for prevention and/or treatment of nephritis.

Abstract: A connector device for coupling a wiper arm and a wiper blade includes a coupling body, a first support portion provided on an upper surface of the coupling body and extending from the coupling body in a form of a cantilever and for applying an elastic restoration force to the wiper arm, a second support portion provided for supporting the wiper arm in a thicknesswise direction of the wiper arm to prevent the wiper arm from moving in the thicknesswise direction, and a third support portion for preventing the wiper arm from moving in a lengthwise direction of the wiper arm, wherein the second support portion is in a form of a hole with closed upper and lower sides and open front and rear sides.

Abstract: A wiper device including: a yoke for supporting a wiper strip; an auxiliary lever including a coupling protrusion coupled to a coupling hole prepared in the yoke and formed of synthetic resin; and a main lever including an assembly protrusion coupled to an assembly hole prepared in the auxiliary lever and formed of the synthetic resin, wherein the auxiliary lever includes: a first vibration prevention portion protrusively formed to contact an upper surface of the yoke on a cross section taken along a width direction of the auxiliary lever in a position where the coupling hole is disposed; and a second vibration prevention portion in which an outer circumference surface of the coupling protrusion is formed in a tapered form so that the coupling protrusion coupled to the coupling hole is fit in a direction in which the coupling protrusion is coupled to the coupling hole.

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract: A semiconductor device includes a trench isolation region provided on a substrate and defining first and second active regions separated from each other. A first semiconductor pillar protruding upward from the first active region is provided. A second semiconductor pillar protruding upward from the second active region is provided. A first gate mask extending to cross over the first and second active regions is provided. The first gate mask surrounds upper sidewalls of the first and second semiconductor pillars. A first gate line formed below the first gate mask, separated from the first and second active regions, and surrounding parts of sidewalls of the first and second semiconductor pillars is provided.

Abstract: A use an extract of Coptidis Rhizoma or a combined extract of Coptidis Rhizoma and Pharbitidis Semen as an active ingredient for preventing and/or treating periodontal disease is provided. The extract of Coptidis Rhizoma or a combined extract of Coptidis Rhizoma and Pharbitidis Semen has activities to stimulate anti-inflammation, osteoblast differentiation and alveolar bone regeneration, and to prevent the alveolar bone destruction, thereby being effective for the prevention and/or treatment of periodontal disease.

Abstract: In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.

Abstract: Disclosed is the outer support member and the inner support member each have a vertical wall and upper and lower horizontal walls. The vertical walls of the outer support member and inner support member are formed on the outer surfaces of the respective support members. The inner edges of the upper and lower horizontal walls are inclined from the rear portions thereof toward front center portions thereof. Thus, the performance of the crash box of the present invention may satisfy the requirements for both an offset test and a barrier test, reduce the weight of the bumper beam assembly to thereby reduce costs, and improve the performance and fuel efficiency of the vehicle.

Abstract: A connector device for coupling a wiper arm and a wiper blade includes a coupling body, a first support portion provided on an upper surface of the coupling body and extending from the coupling body in a form of a cantilever and for applying an elastic restoration force to the wiper arm, a second support portion provided for supporting the wiper arm in a thicknesswise direction of the wiper arm to prevent the wiper arm from moving in the thicknesswise direction, and a third support portion for preventing the wiper arm from moving in a lengthwise direction of the wiper arm, wherein the second support portion is in a form of a hole with closed upper and lower sides and open front and rear sides.

Abstract: A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

Abstract: A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties.

Abstract: In a semiconductor device and a method of manufacturing the same, a first insulation layer is removed from a cell area of a substrate and a first active pattern is formed on the first area by a laser-induced epitaxial growth (LEG) process. Residuals of the first insulation layer are passively formed into a first device isolation pattern on the first area. The first insulation layer is removed from the second area of the substrate and a semiconductor layer is formed on the second area of the substrate by a SEG process. The semiconductor layer on the second area is patterned into a second active pattern including a recessed portion and a second insulation pattern in the recessed portion is formed into a second device isolation pattern on the second area. Accordingly, grain defects in the LEG process and lattice defects in the SEG process are mitigated or eliminated.

Abstract: A wafer temporary bonding method using silicon direct bonding (SDB) may include preparing a carrier wafer and a device wafer, adjusting roughness of a surface of the carrier wafer, and combining the carrier wafer and the device wafer using the SDB. Because the method uses SDB, instead of an adhesive layer, for a temporary bonding process, a module or process to generate and remove an adhesive is unnecessary. Also, a defect in a subsequent process, for example, a back-grinding process, due to irregularity of the adhesive may be prevented.

Abstract: A vertical pillar semiconductor device may include a substrate, a group of channel patterns, a gate insulation layer pattern and a gate electrode. The substrate may be divided into an active region and an isolation layer. A first impurity region may be formed in the substrate corresponding to the active region. The group of channel patterns may protrude from a surface of the active region and may be arranged parallel to each other. A second impurity region may be formed on an upper portion of the group of channel patterns. The gate insulation layer pattern may be formed on the substrate and a sidewall of the group of channel patterns. The gate insulation layer pattern may be spaced apart from an upper face of the group of channel patterns. The gate electrode may contact the gate insulation layer and may enclose a sidewall of the group of channel patterns.