Abstract: A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier driving signals in response to a mat enable signal, a sense amplifier enable signal and a power-up signal; a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect first and second sense amplifier driving nodes to cause the first and second sense amplifier driving nodes to have substantially the same voltage level, or disconnect the first and second sense amplifier driving nodes to apply first and second sense amplifier driving voltages to the first and second sense amplifier driving nodes; and a sense amplifier configured to be applied with the first and second sense amplifier driving voltages, and sense and amplify a voltage difference of a bit line and a bit line bar.

Abstract: A semiconductor device includes a memory cell array including a normal memory cell array and a redundancy memory cell array, a normal refresh counter suitable for generating a normal address for performing a refresh operation to the normal memory cell array with a first period during a refresh mode and a redundancy refresh counter suitable for generating a redundancy address for performing a refresh operation to the redundancy memory cell with a second period shorter than the first period.

Abstract: A memory device comprises a cell array having a plurality of word lines, an address counting unit suitable for generating a counting address that is changed whenever one or more of the plurality of word lines are refreshed, and a control unit suitable for selecting a word line corresponding to the counting address among the plurality of word lines and refreshing the selected word line within a first period in response to a refresh command during a first operation mode, within a second period that is longer than the first period during a second operation mode, and within a third period that is shorter than the second period in a high frequency section after the second operation mode begins.

Abstract: A self refresh pulse generation circuit includes a control signal generator configured to generate a control signal asserted for an initial period of a self refresh mode, and a self refresh pulse generator configured to generate a self refresh pulse having a period controlled in response to the control signal, in the self refresh mode.

Abstract: A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier driving signals in response to a mat enable signal, a sense amplifier enable signal and a power-up signal; a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect first and second sense amplifier driving nodes to cause the first and second sense amplifier driving nodes to have substantially the same voltage level, or disconnect the first and second sense amplifier driving nodes to apply first and second sense amplifier driving voltages to the first and second sense amplifier driving nodes; and a sense amplifier configured to be applied with the first and second sense amplifier driving voltages, and sense and amplify a voltage difference of a bit line and a bit line bar.

Abstract: A self refresh pulse generation circuit includes a control signal generator configured to generate a control signal asserted for an initial period of a self refresh mode, and a self refresh pulse generator configured to generate a self refresh pulse having a period controlled in response to the control signal, in the self refresh mode.

Abstract: A self-refresh test circuit includes a test clock generation unit, a pulse generation unit, a period signal selection unit, and a self-refresh pulse control unit. The test clock generation unit divides a clock signal to generate a plurality of divided clock signals having different periods when a test enable signal is enabled, and outputs one of the plurality of divided clock signals as a selected clock signal. The pulse generation unit generates a test period signal in response to the selected clock signal. The period signal selection unit outputs one of the test period signal and a self-refresh period signal as a selected period signal. The self-refresh pulse control unit generates a self-refresh pulse in response to a self-refresh exit signal and the selected period signal.

Abstract: A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

Abstract: A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

Abstract: A self-refresh test circuit includes a test clock generation unit, a pulse generation unit, a period signal selection unit, and a self-refresh pulse control unit. The test clock generation unit divides a clock signal to generate a plurality of divided clock signals having different periods when a test enable signal is enabled, and outputs one of the plurality of divided clock signals as a selected clock signal. The pulse generation unit generates a test period signal in response to the selected clock signal. The period signal selection unit outputs one of the test period signal and a self-refresh period signal as a selected period signal. The self-refresh pulse control unit generates a self-refresh pulse in response to a self-refresh exit signal and the selected period signal.

Abstract: A refresh control apparatus is provided which is capable of dispersing a peak current at an all-bank refresh mode and reducing the characteristic difference between the banks. The refresh control apparatus includes an internal refresh counter for outputting row address signals to select word lines when a refresh command is inputted from an external circuit, a row decoder for outputting row decoding signals to select all banks in response bank active signals and the row address signals, an enable signal control unit for sequentially outputting at a time interval sense amplifier enable signals in response to the bank active signals and the refresh command, and a sense amplifier for sequentially refreshing all of the banks at a time interval in response to the sense amplifier enable signals.

Abstract: An auto-refresh control apparatus is provided which includes a counter unit for outputting counter signals in response to an external auto-refresh command signal, and a refresh command signal generating unit for generating internal auto-refresh command signals in response to the counter signals when a test mode signal is activated.

Abstract: Disclosed herein is a process of preparing octafluorocyclohexadiene using hexafluorobenzene as a raw material. The hexafluorobenzene reacts with an activated fluorinating agent at 60-200° C. in an inert gas atmosphere. The activated fluorinating agent is prepared by mixing 1-10 wt % of cobalt difluoride with 90-99 wt % of other metal fluoride selected from the group of calcium fluoride, magnesium fluoride, aluminum fluoride, sodium fluoride and potassium fluoride. The mixture reacts with fluorine gas at 200-400° C.

Abstract: A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

Abstract: A refresh control apparatus is provided which is capable of dispersing a peak current at an all-bank refresh mode and reducing the characteristic difference between the banks. The refresh control apparatus includes an internal refresh counter for outputting row address signals to select word lines when a refresh command is inputted from an external circuit, a row decoder for outputting row decoding signals to select all banks in response bank active signals and the row address signals, an enable signal control unit for sequentially outputting at a time interval sense amplifier enable signals in response to the bank active signals and the refresh command, and a sense amplifier for sequentially refreshing all of the banks at a time interval in response to the sense amplifier enable signals.

Abstract: An auto-refresh control apparatus is provided which includes a counter unit for outputting counter signals in response to an external auto-refresh command signal, and a refresh command signal generating unit for generating internal auto-refresh command signals in response to the counter signals when a test mode signal is activated.

Abstract: A row active control circuit of a PSRAM controls a refresh timing when a refresh operation is performed before activation of a row path for embodiment of a page mode, thereby preventing mis-operations. The row active signal generating unit generates a row active signal when an active condition is set by the internal active signal. The internal active signal generating unit generates the internal active signal in response to a refresh start signal. The row active control unit generates a row active standby signal with the row active signal in response to the internal active signal. The external active signal generating unit for generating an external active control signal in response to the row active standby signal.

Abstract: A semiconductor memory integrated circuit for controlling a refresh operation includes: a first period generating unit that generates a first periodic signal having an uniformed period; a second period generating unit that generates a second periodic signal according to a first control signal; a period generation control unit that generates a timing signal for every predetermined period; a frequency dividing unit that divides the frequency of the first periodic signal into at least one frequency-divided periodic signals; and a period selection control unit that controls the operation of the second period generating unit according to the at least one frequency-divided periodic signals and the second periodic signal, determines temperature, and outputs one of the frequency-divided periodic signals corresponding to the determined temperature as a refresh signal.

Abstract: The invention is a method for continuously preparing highly pure octafluorocyclopentene for use in dry-etching processes. The method includes reacting octachlorocyclopentene with KF in a continuous manner, and purifying crude octafluorocyclopentene. In the reacting step, two KF-charged filters are installed in parallel and allowed to communicate with a reactor containing octachlorocyclopentene in an alternating manner to produce crude octafluorocyclopentene. In the purifying step, organics having lower boiling points than octafluorocyclopentene are removed, and metal ingredients and organics having boiling points higher than octafluorocyclopentene are separated to recover octafluorocyclopentene as a gas. The gaseous octafluorocyclopentene composition contains C5F8 in an amount of 99.995 vol % or higher, nitrogen in an amount of 50 vol ppm or less, oxygen in an amount of 5 vol ppm or less, water in an amount of 5 vol ppm or less, and metal ingredients in an amount of 5 wt ppb or less.

Abstract: A power line control circuit of a semiconductor device in which a width of a power line can be selectively controlled. The power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power line employing the dummy power line. It is therefore possible to easily change the width of the power lines and to reduce the manufacturing cost and the manufacturing time depending on the formation of the power lines. Furthermore, the power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power lines, if appropriate. Accordingly, mesh of optimized power lines can be provided. Furthermore, more stabilized product characteristics can be secured and the yield of semiconductor memory devices can be enhanced.