DATA OUTPUT CIRCUIT IN A SEMICONDUCTOR MEMORY APPARATUS

Abstract

A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

Description

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. 119(a) to Korean application number 10-2008-0078394, filed on Aug. 11, 2008, in the Korean Patent Office, which is incorporated by reference in its entirety as if set forth in full.

TECHNICAL FIELD

The embodiments described herein relate to a semiconductor memory apparatus and, more particularly, to a data output circuit in a semiconductor memory apparatus.

RELATED ART

Generally, a semiconductor memory apparatus outputs data to an external circuit using a data output circuit. The data output circuit amplifies the data and then outputs the amplified data to an outside of the semiconductor memory apparatus; however, a stable buffering operation is inevitably required to output the data because the semiconductor memory apparatus is required to operate in a high-speed and low-power consumption.

On the other hand, in the semiconductor memory apparatus, a data amplification strength is being increasingly reduced from a full size strength to a half or quarter size strength in order to reduce current consumption. Therefore, data valid window to output the data is also being increasingly reduced.

FIG. 1 is a schematic circuit diagram illustrating a conventional data output circuit.

Referring to FIG. 1, the conventional data output circuit includes a pre-driving unit 10, a pull-up driver 20, a pull-down driver 30, and a pad 40. The pre-driving unit 10 includes a first pre-driver 11 to produce a pull-up signal ‘up_in’ and a second pre-driver 12 to produce a pull-down signal ‘down_in’. The first and second pre-drivers 11 and 12 receive input data ‘Din’ and produce the pull-up signal ‘up_in’ and the pull-down signal ‘down_in’, which are respectively applied to the pull-up driver 20 and the pull-down driver 30, after amplifying the received signals.

The pull-up driver 20 performs a pull-up operation on a first node A in response to the pull-up signal ‘up_in’ of the first pre-driver 11 and the pull-down driver 30 performs a pull-down operation on a second node B in response to the pull-down signal ‘down_in’ of the second pre-driver 12. The pull-up driver 20 including three PMOS transistors P1, P2 and P3, to which an external power supply voltage ‘VDDQ’ is applied, pull-up drives the first node A. The pull-down driver 30 including three NMOS transistors N1, N2 and N3, to which are connected to a ground voltage terminal ‘VSSQ’, pull-down drives the second node B.

The pad 40, which receive output signals ‘up_out’ and ‘down_out’ on the first and second nodes A and B, provides output data ‘Dout’ to an external circuit.

The PMOS transistors P1, P2 and P3 in the pull-up driver 20 and the NMOS transistors N1, N2 and N3 in the pull-down driver 30 drive the first and second nodes A and B in response to the pull-up signal ‘up_in’ and the pull-down signal ‘down_in’ respectively; however, their driving force is reduced significantly after a predetermined time. That is, the voltage (Vgs) between a gate terminal and a source terminal in each transistor is reduced such that the drivability is also reduced. This is linked directly with the reduction of the valid data window. The valid data window can be increased by increasing the number of the transistors in the pull-up and pull-down drivers; however, this causes another problem in that the upper and lowest limits of the output data can be exceeded.

The reduction of the range in the valid data window may cause a device failure in all the applications. Therefore, it is very important to guarantee the characteristics of a data output circuit which has a stable valid data window.

SUMMARY

A data output circuit capable of increasing a range of a valid data window is described herein.

According to one aspect, a data output circuit in a semiconductor memory apparatus comprises a pre-driving unit configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driving unit configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driving unit configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

According to another aspect, a data output circuit in a semiconductor memory apparatus comprises a pre-driving unit configured to receive input data and then produce a pull-up signal and a pull-down signal, a first switching unit configured to produce an inverted signal of a voltage level on a first node in response to the pull-up signal, a pull-up driving unit configured to pull-up drive the first node in response to the pull-up signal and additionally pull-up drive the first node in response to an output signal of the first switching unit, a second switching unit configured to produce an inverted signal of a voltage level on a second node in response to the pull-down signal, a pull-down driving unit configured to pull-down drive the second node in response to the pull-down signal and additionally pull-down drive the second node in response to an output signal of the second switching unit, and a pad coupled to the first and second nodes to generate output data.

In the present disclosure, a data output circuit is improved by enlarging the valid data window of output data.

These and other features, aspects, and embodiments are described below in the section entitled “Detailed Description.”

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic circuit diagram illustrating a conventional data output circuit;

FIG. 2 is a schematic block diagram illustrating an example of a structure of a data output circuit of a semiconductor memory apparatus according to one embodiment;

FIG. 3 is a circuit diagram illustrating the data output circuit of FIG. 2; and

FIG. 4 is a view showing a comparison of two ranges of valid data windows of output data according to the prior art and the present disclosure.

DETAILED DESCRIPTION

FIG. 2 is a schematic block diagram illustrating an example of a structure of a data output circuit of a semiconductor memory apparatus according to one embodiment.

Referring to FIG. 2, the data output circuit according to one embodiment can include a pre-driving unit 10, a pull-up driving unit 200, a pull-down driving unit 300, and a pad 40.

The pre-driving unit 10 receives input data ‘Din’ and then produces a pull-up signal ‘up_in’ and a pull-down signal ‘down_in’. The pre-driving unit 10 can include a first pre-driver 11 to produce the pull-up signal ‘up_in’ in response to the input data ‘Din’ and a second pre-driver 12 to produce the pull-down signal ‘down_in’ in response to the input data ‘Din’. The first and second pre-drivers 11 and 12 can be implemented by the conventional pre-drivers. Typically, they can be implemented by a circuit which amplifies the input data ‘Din’ such as a buffer.

The pull-up driving unit 200 pulls up a voltage level on a first node A in response to the pull-up signal ‘up_in’ and provides an additional pull-up drive at the time the voltage level on the first node A transitions (e.g., switches). That is, the pull-up driving unit 200 can include a first main driver 210 to pull-up drive the first node A in response to the pull-up signal ‘up_in’ and further include a first sub driver 220 to additionally pull-up drive the first node A at the time the voltage level on the first node A transitions.

The pull-down driving unit 300 pulls down a voltage level on a second node B in response to the pull-down signal ‘down_in’ and provides an additional pull-down drive at the time the voltage level on the second node B transitions. That is, the pull-down driving unit 300 can include a second main driver 310 to pull-down drive the second node B in response to the pull-down signal ‘down_in’ and further include a second sub driver 320 to additionally pull-down drive the second node N at the time the voltage level on the second node A transitions.

The pad 40 is coupled to the first and second nodes A and B and then receives output signals from the first and second nodes A and B. The pad 40 outputs output data ‘Dout’ to an external circuit by buffering output signals ‘up_out’ and ‘down_out’. The pad 40 can be implemented by conventional pad circuits.

FIG. 3 is a circuit diagram illustrating the pull-up driving unit 200 and the pull-down driving unit 300 of FIG. 2. Referring to FIG. 3, the data output circuit according to one embodiment will be described in detail.

The first main driver 210 can include a plurality of PMOS transistors P1, P2 and P3 each of which has a gate receiving the pull-up signal ‘up_in,’ a source receiving an external power supply voltage ‘VDDQ,’, and a drain coupled to the first node A. In one embodiment, the first main driver 210 includes, without being limited to, for example, three transistors P1, P2 and P3.

The first sub driver 220 may include a first switching unit 221 and a first driver 222 in order that the first node A is further pull-up driven at the time the voltage level on the first node A transitions. The first switching unit 221 is turned on/off in response to the pull-up signal ‘up_in’ and produces, as a first sub driving signal ‘subup_in’, an inverted signal of the voltage on the first node A. The first driver 222 pull-up drives the first node A in response to the first sub driving signal ‘subup_in’.

The first switching unit 221 is turned on/off in response to the pull-up signal ‘up_in’ and can include a first tri-state inverter to produce, as the first sub driving signal ‘subup_in’, the inverted signal of the voltage on the first node A. The first tri-state inverter can include two PMOS transistors Pi1 and Pi2 and two NMOS transistors Ni1 and Ni2.

The first driver 222 can include a PMOS transistor Pd having a gate to which the first sub driving signal ‘subup_in’ is applied, a source to which the external power supply voltage ‘VDDQ’ is applied, and a drain coupled to the first node A.

The second main driver 310 may include a plurality of NMOS transistors N1, N2 and N3 each of which has a gate receiving the pull-down signal ‘down_in,’ is applied, a source receiving a ground voltage ‘VSSQ,’ and a drain coupled to the second node B. In one embodiment, the second main driver 310 includes, without being limited to, for example, three transistors N1, N2 and N3.

The second sub driver 320 can include a second switching unit 321 and a second driver 322 in order that the second node B is further pull-down driven at the time the voltage level on the second node B transitions. The second switching unit 321 is turned on/off in response to the pull-down signal ‘down_in’ and produces, as a second sub driving signal ‘subdown_in’, an inverted signal of the voltage on the second node B. The second driver 322 pull-down drives the second node B in response to the second sub driving signal ‘subdown_in’.

The second switching unit 321 is turned on/off in response to the pull-up signal ‘down_in’ and can include a second tri-state inverter to produce, as the second sub driving signal ‘subdown_in’, the inverted signal of the voltage on the second node B. In similar to the first tri-state inverter, the second tri-state inverter can include two PMOS transistors Pi3 and Pi4 and two NMOS transistors Ni3 and Ni4.

The second driver 322 can include an NMOS transistor Nd having a gate receiving the second sub driving signal ‘subdown_in,’ a source receiving the ground voltage ‘VSSQ’ and a drain coupled to the second node B.

The first and second pre-drivers 11 and 12 and the pad 40 can be implemented by conventional pre-drivers and pad circuits, respectively. Accordingly, detailed description will be omitted in the present disclosure.

Referring FIGS. 2 and 3, the operation of the data output circuit according to one embodiment will described below.

First, when the input data ‘Din’ is in a high level, the first and second pre-drivers 11 and 12 produce the pull-up signal ‘up_in’ and the pull-down signal ‘down_in’ of a high level by amplifying the input data ‘Din’. Accordingly, the PMOS transistors P1, P2 and P3 in the first main driver 210 are turned off and the NMOS transistors N1, N2 and N3 in the second main driver 310 are turned on. The turn-on NMOS transistors N1, N2 and N3 drive the second node B to the ground voltage level ‘VSSQ’. Therefore, the output signal ‘down_out’ of a low level is gradually produced on the second node B. Meanwhile, the second switching unit 321, which receives the pull-down signal ‘down_in’ of a high level and an inverted signal via the second inverter IV2 of the pull-down signal ‘down_in’, is turned on. However, the second switching unit 321 still produces the second sub driving signal ‘subdown_in’ with a disabled voltage, before the output signal ‘down_out’ on the second node B transitions to a low level. The second switching unit 321 produces the second sub driving signal ‘subdown_in’ with an enabled voltage level, at the time the second main driver 310 pull-down drives the second node B and the output signal ‘down_out’ on the second node B transitions to a low level. Accordingly, the second driver 322, which receives the enable voltage level of the second sub driving signal ‘subdown_in’, additionally pull-down drives the second node B.

While the NMOS transistors N1, N2 and N3 in the second main driver 310 pull-down drive the second node B in response to the pull-down signal ‘down_in’, the source voltage of the second main driver 310, i.e., the voltage level of the ground voltage ‘VSSQ’, is continuously increased. Accordingly, gate to source voltages (Vgs) are continuously decreased in the NMOS transistors N1, N2 and N3 and this causes a drop of the pull-down drive in the NMOS transistors N1, N2 and N3. Therefore, when the drive of the NMOS transistors N1, N2 and N3 is decreased, the second node B additionally pulled down by the second driver 322.

In contrast, when the input data ‘Din’ are in a low level, the first and second pre-drivers 11 and 12 produce the pull-down signal ‘down_in’ and the pull-up signal ‘up_in’ of a low level by amplifying the input data ‘Din’. Accordingly, the PMOS transistors P1, P2 and P3 in the first main driver 210 are turned on and the NMOS transistors N1, N2 and N3 in the second main driver 310 are turned off. The turned-on PMOS transistors P1, P2 and P3 drive the first node A up to the external power supply voltage ‘VDDQ’. Therefore, the output signal ‘up_out’ of a high level is gradually produced at the first node A. Meanwhile, the first switching unit 221, which receives the pull-up signal ‘up_in’ of a low level and an inverted signal via the first inverter IV1 of the pull-up signal ‘up_in’, is turned on. However, the first switching unit 221 still produces the first sub driving signal ‘subup_in’ with a disabled voltage level before the output signal ‘up_out’ on the first node A transitions to a high level. The first switching unit 221 produces the first sub driving signal ‘subup_in’ with an enabled voltage level at the time the first main driver 210 pull-up drives the first node A and the output signal ‘up_out’ on the first node A transitions to a high level. Accordingly, the first driver 222, which receives the enabled voltage level of the first sub driving signal ‘subup_in’, additionally pull-up drives the first node A.

While the PMOS transistors P1, P2 and P3 in the first main is driver 210 pull-up drive the first node A in response to the pull-up signal ‘up_in’, the source voltage of the first main driver 210, i.e., the voltage level of the external power supply voltage ‘VDDQ’, is continuously decreased. Accordingly, gate to source voltages (Vgs) are continuously decreased in the PMOS transistors P1, P2 and P3 and this causes a drop of the pull-up drive in the PMOS transistors P1, P2 and P3. Therefore, when the drive of the PMOS transistors P1, P2 and P3 is decreased, the first node A is additionally pull-up driven by the first driver 222.

FIG. 4 is a view showing a comparison of two ranges of valid data windows of output data according to the prior art and the present disclosure.

The data output circuit according to the present disclosure includes the first and second sub drivers 222 and 322 and then provides the additional pull-up drive and pull-down drive when the gate to source voltage (Vgs) is decreased at the transistors P1 to P3 and N1 to N3 in the first and second main drivers 210 and 310, thereby increasing the valid data window. As shown in FIG. 4, the valid data window according to the present disclosure is wider than that according to the prior art.

While certain embodiments have been described above, it will be understood that the embodiments described are by way of example only. Accordingly, the systems and methods described herein should not be limited based on the described embodiments. Rather, the systems and methods described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.

Claims

1-22. (canceled)

23. A data output circuit comprising:

a driver including a main driver configured to drive an output node in response to an input signal and a sub driver configured to additionally drive the output node in response to an inverted signal obtained by inverting a voltage level on the output node; and

an output unit coupled to the output node to generate an output data.

24. The data output circuit of claim 23, wherein the sub driver includes:

a switching unit configured to generate the inverted signal in response to the input signal; and

a driving unit configured to drive the output node in response to the inverted signal.

25. The data output circuit of claim 24, wherein the switching unit includes a tri-state inverter which is configured to generate the inverted signal.

26. The data output circuit of claim 23, wherein the sub driver drives the output node when the voltage level of the output node transits.

27. The data output circuit of claim 23, wherein if the input signal is a logic high state, the main driver and the sub driver drive the output node to logic high state.

28. The data output circuit of claim 23, wherein if the input signal is a logic low state, the main driver and the sub driver drive the output node to logic low state.

29. The data output circuit of claim 23, wherein the output unit includes a pad outputting the output data to an external circuit.

30. The data output circuit of claim 23, wherein the output unit includes a buffer unit buffering the output data.

31. The data output circuit comprising:

a pre-driving unit configured to generate an input signal in response to an input data;

a driver including a main driver configured to drive an output node in response to the input signal and a sub driver configured to additionally drive the output node in response to an inverted signal obtained by inverting a voltage level on the output node; and

an output unit coupled to the output node to generate an output data.

32. The data output circuit of claim 31, wherein the sub driver includes:

a switching unit configured to generate the inverted signal in response to the input signal; and

a driving unit configured to drive the output node in response to the inverted signal.

33. The data output circuit of claim 32, wherein the switching unit includes a tri-state inverter which is configured to generate the inverted signal.

34. The data output circuit of claim 31, wherein the pre-driving unit generates a logic high signal or a logic low signal in response to the input data.

35. The data output circuit of claim 34, wherein the main driver and the sub driver drive the output node to logic high state in response to the logic high signal.

36. The data output circuit of claim 35, wherein the main driver includes a plurality of PMOS transistors each of which has a gate receiving the logic high signal, a source receiving an external power supply voltage, and a drain coupled to the output node.

37. The data output circuit of claim 35, wherein the sub driver includes a PMOS transistor having a gate receiving the inverted signal, a source receiving an external power supply voltage, and a drain coupled to the output node.

38. The data output circuit of claim 34, wherein the main driver and sub driver drive the output node to logic low state in response to the logic low signal.

39. The data output circuit of claim 38, wherein the main driver includes a plurality of NMOS transistors each of which has a gate receiving the logic low signal, a source receiving a ground voltage, and a drain coupled to the output node.

40. The data output circuit of claim 38, wherein the sub driver includes a NMOS transistor having a gate receiving the inverted signal, a source receiving a ground voltage, and a drain coupled to the output node.

41. The data output circuit of claim 31, wherein the sub driver drives the output node when the voltage level of the output node transits.

42. The data output circuit of claim 31, wherein the output unit includes a pad outputting the output data to an external circuit.

43. The data output circuit of claim 31, wherein the output unit includes a buffer unit buffering the output data.

44. A data output circuit comprising:

a pre-driving unit configured to generate a pull-up signal in response to an input data; and

a pull-up driver including a first main driver configured to drive a first node to logic high state in response to the pull-up signal and a first sub driver configured to additionally drive the first node to logic high state in response to a first inverted signal obtained by inverting a voltage level on the first node.

45. The data output circuit of claim 44, wherein the first sub driver includes:

a first switching unit configured to generate the first inverted signal in response to the pull-up signal; and

a first driving unit configured to drive the first node to logic high state in response to the first inverted signal.

46. The data output circuit of claim 45, wherein the first switching unit includes a first tri-state inverter which is configured to generate the first inverted signal.

47. The data output circuit of claim 46, wherein the first tri-state inverter is turned on by the pull-up signal.

48. The data output circuit of claim 45, wherein the first driving unit includes a PMOS transistor having a gate receiving the first inverted signal, a source receiving an external power supply voltage, and a drain coupled to the first node.

49. The data output circuit of claim 44, wherein the first main driver includes a plurality of PMOS transistors each of which has a gate receiving the pull-up signal, a source receiving an external power supply voltage, and a drain coupled to the first node.

50. The data output circuit of claim 44, wherein the pre-driving unit is configured to generate a pull-down signal in response to the input data.

51. The data output circuit of claim 50, further comprising:

a pull-down driver including a second main driver configured to drive a second node to logic low state in response to the pull-down signal and a second sub driver configured to additionally drive the second node to logic low state in response to a second inverted signal obtained by inverting a voltage level on the second node.

52. The data output circuit of claim 51, wherein the second sub driver includes:

a second switching unit configured to generate the second inverted signal in response to the pull-down signal; and

a second driving unit configured to drive the second node to logic low state in response to the second inverted signal.

53. The data output circuit of claim 52, wherein the second switching unit includes a second tri-state inverter which is configured to generate the second inverted signal.

54. The data output circuit of claim 53, wherein the second tri-state inverter is turned on by the pull-down signal.

55. The data output circuit of claim 52, wherein the second driving unit includes a NMOS transistor having a gate receiving the second inverted signal, a source receiving a ground voltage, and a drain coupled to the second node.

56. The data output circuit of claim 51, wherein the second main driver includes a plurality of NMOS transistors each of which has a gate receiving the pull-down signal, a source receiving a ground voltage, and a drain coupled to the second node.

57. The data output circuit of claim 51, wherein the first sub driver drives the first node when the voltage level of the first node transitions, and

wherein the second sub driver drives the second node when the voltage level of the second node transitions.

58. The data output circuit of claim 51, further comprising:

an output unit coupled to the first node and the second node to generate an output data.

59. The data output circuit of claim 50, wherein the pre-driving unit includes:

a first pre-driver configured to generate the pull-up signal in response to the input data; and

a second pre-driver configured to generate the pull-down signal in response to the input data.