Patents by Inventor Jong-Jin Lee

Jong-Jin Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250190039
    Abstract: Disclosed is a system-on-chip. The system-on-chip including at least one operation processing unit configured to process an instruction based on a driving voltage and a clock signal, a temperature management module configured to estimate a cooling coefficient and a heating coefficient associated with the at least one operation processing unit based on a temperature measured at the at least one operation processing unit, and determine an operating frequency of the clock signal to be sent to the at least one operation processing unit based on the cooling coefficient and the heating coefficient, and a dynamic voltage and frequency scaling (DVFS) module configured to output a control signal for adjusting the driving voltage and the clock signal based on the operating frequency.
    Type: Application
    Filed: July 1, 2024
    Publication date: June 12, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seokwon LEE, Jong-Jin LEE
  • Patent number: 11985580
    Abstract: An electronic device includes a narrowband internet of things (NB-IoT) circuit; a shared central processor to control the narrowband internet of things circuit; a shared memory to store data or code from the shared central processor; and a communicator controlled by the shared central processor. The communicator stores the data or the code in the shared memory.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: May 14, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo Young Choi, Dong Yun Kim, Ivan Galkin, Ji-Hoon Park, Jong-Jin Lee
  • Publication number: 20230345219
    Abstract: An electronic device includes a narrowband internet of things (NB-IoT) circuit; a shared central processor to control the narrowband internet of things circuit; a shared memory to store data or code from the shared central processor; and a communicator controlled by the shared central processor. The communicator stores the data or the code in the shared memory.
    Type: Application
    Filed: June 27, 2023
    Publication date: October 26, 2023
    Inventors: Woo Young CHOI, Dong Yun KIM, Ivan GALKIN, Ji-Hoon PARK, Jong-Jin LEE
  • Patent number: 11700519
    Abstract: An electronic device includes a narrowband internet of things (NB-IoT) circuit; a shared central processor to control the narrowband internet of things circuit; a shared memory to store data or code from the shared central processor; and a communicator controlled by the shared central processor. The communicator stores the data or the code in the shared memory.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: July 11, 2023
    Inventors: Woo Young Choi, Dong Yun Kim, Ivan Galkin, Ji-Hoon Park, Jong-Jin Lee
  • Publication number: 20220303742
    Abstract: An electronic device includes a narrowband internet of things (NB-IoT) circuit; a shared central processor to control the narrowband internet of things circuit; a shared memory to store data or code from the shared central processor; and a communicator controlled by the shared central processor. The communicator stores the data or the code in the shared memory.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 22, 2022
    Inventors: Woo Young CHOI, Dong Yun KIM, Ivan GALKIN, Ji-Hoon PARK, Jong-Jin LEE
  • Patent number: 11368829
    Abstract: An electronic device includes a narrowband internet of things (NB-IoT) circuit; a shared central processor to control the narrowband internet of things circuit; a shared memory to store data or code from the shared central processor; and a communicator controlled by the shared central processor. The communicator stores the data or the code in the shared memory.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: June 21, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Young Choi, Dong Yun Kim, Ivan Galkin, Ji-Hoon Park, Jong-Jin Lee
  • Publication number: 20200389776
    Abstract: An electronic device includes a narrowband internet of things (NB-IoT) circuit; a shared central processor to control the narrowband internet of things circuit; a shared memory to store data or code from the shared central processor; and a communicator controlled by the shared central processor. The communicator stores the data or the code in the shared memory.
    Type: Application
    Filed: December 3, 2019
    Publication date: December 10, 2020
    Inventors: Woo Young CHOI, Dong Yun KIM, Ivan GALKIN, Ji-Hoon PARK, Jong-Jin LEE
  • Patent number: 10734309
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Tsukasa Matsuda, Rak-Hwan Kim, Byung-Hee Kim, Nae-In Lee, Jong-Jin Lee
  • Patent number: 10700164
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Patent number: 10697101
    Abstract: A motor for a washing machine includes a stator and a rotor. The rotor includes a rotor casing including a base portion formed in a disk shape and a vertical wall extending substantially perpendicularly from an outer periphery of the base portion, a permanent magnet provided on an inner surface of the vertical wall of the rotor casing, and a connecting member provided at a center of the base portion of the rotor casing and connected to a shaft. The base portion of the rotor casing includes a first ring portion facing a coil portion of the stator and a second ring portion, provided with a plurality of air inlet holes, that is positioned between the first ring portion and the connecting member and does not face the coil portion of the stator.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-woo Cho, Jong-jin Lee, Jin-sol Je, Tae-sang Park, Woon-yong Lee
  • Patent number: 10525151
    Abstract: A method for preparing a radiopharmaceutical and, specifically, a method for preparing an organic fluoride-aliphatic compound usable as a radiopharmaceutical, a method for purifying the prepared organic fluoride-aliphatic compound, and a method for preparing a radiopharmaceutical by using a cassette comprising a backdraft preventing reaction container. A method for preparing an organic fluorinated aliphatic compound includes allowing a fluorine salt to react with a leaving group-containing aliphatic compound by using a multifunctional solvent represented by the following Chemical Formula 1 to obtain an aliphatic compound labeled with [18F] fluoride substituting for the leaving group. The organic fluoride-aliphatic compound can be prepared and purified through even a simple process at high yield, high efficiency, and high purity, and the radiopharmaceutical can be safely prepared without damage to a synthetic apparatus.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: January 7, 2020
    Assignee: THE ASAN FOUNDATION
    Inventors: Sang-ju Lee, Seung-jun Oh, Dae-hyuk Moon, Jin-sook Ryu, Jae-seung Kim, Jong-jin Lee
  • Patent number: 10332791
    Abstract: A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench. The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer. The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Yun Jeon, Rak-Hwan Kim, Byung-Hee Kim, Kyoung-Hee Nam, Jong-Jin Lee, Jae-Won Hwang
  • Publication number: 20190189540
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.
    Type: Application
    Filed: February 22, 2019
    Publication date: June 20, 2019
    Inventors: Jin-Nam Kim, Tsukasa MATSUDA, Rak-Hwan KIM, Byung-Hee KIM, Nae-In LEE, Jong-Jin LEE
  • Publication number: 20190189744
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Application
    Filed: February 13, 2019
    Publication date: June 20, 2019
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Patent number: 10217820
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Publication number: 20180158730
    Abstract: A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench, The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer, The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.
    Type: Application
    Filed: November 7, 2017
    Publication date: June 7, 2018
    Inventors: Ho-Yun Jeon, Rak-Hwan Kim, Byung-Hee Kim, Kyoung-Hee Nam, Jong-Jin Lee, Jae-Won Hwang
  • Publication number: 20180127909
    Abstract: A motor for a washing machine includes a stator and a rotor. The rotor includes a rotor casing including a base portion formed in a disk shape and a vertical wall extending substantially perpendicularly from an outer periphery of the base portion, a permanent magnet provided on an inner surface of the vertical wall of the rotor casing, and a connecting member provided at a center of the base portion of the rotor casing and connected to a shaft. The base portion of the rotor casing includes a first ring portion facing a coil portion of the stator and a second ring portion, provided with a plurality of air inlet holes, that is positioned between the first ring portion and the connecting member and does not face the coil portion of the stator.
    Type: Application
    Filed: August 9, 2017
    Publication date: May 10, 2018
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-woo CHO, Jong-jin LEE, Jin-sol JE, Tae-sang PARK, Woon-yong LEE
  • Publication number: 20170358519
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom suffice of the first trench.
    Type: Application
    Filed: August 4, 2017
    Publication date: December 14, 2017
    Inventors: Jin-Nam Kim, Tsukasa Matsuda, Rak-Hwan Kim, Byung-Hee Kim, Nae-In Lee, Jong-Jin Lee
  • Publication number: 20170319720
    Abstract: A method for preparing a radiopharmaceutical and, specifically, a method for preparing an organic fluoride-aliphatic compound usable as a radiopharmaceutical, a method for purifying the prepared organic fluoride-aliphatic compound, and a method for preparing a radiopharmaceutical by using a cassette comprising a backdraft preventing reaction container. A method for preparing an organic fluorinated aliphatic compound includes allowing a fluorine salt to react with a leaving group-containing aliphatic compound by using a multifunctional solvent represented by the following Chemical Formula 1 to obtain an aliphatic compound labeled with [18F] fluoride substituting for the leaving group. The organic fluoride-aliphatic compound can be prepared and purified through even a simple process at high yield, high efficiency, and high purity, and the radiopharmaceutical can be safely prepared without damage to a synthetic apparatus.
    Type: Application
    Filed: November 6, 2015
    Publication date: November 9, 2017
    Inventors: Sang-ju LEE, Seung-jun OH, Dae-hyuk MOON, Jin-sook RYU, Jae-seung KIM, Jong-jin LEE
  • Publication number: 20170294337
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Application
    Filed: June 26, 2017
    Publication date: October 12, 2017
    Inventors: Jin-Nam KIM, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung