Abstract: A die coater system configured for coating a foil with an active material includes a die block assembly with at least one discharge port configured to dispense an active material slurry onto the foil, the discharge port defining a discharge direction and extending in a lateral direction; and at least one adjustment device coupled to a back side of the die block assembly opposite to the at least one discharge port, the at least one adjustment device including an actor configured to urge at least a section of the die block assembly forwards or backwards in the discharge direction.

Abstract: A display device includes a first substrate and a second substrate facing each other; and a filling layer disposed between the first substrate and the second substrate. The first substrate comprises a support substrate comprising a display area in which emission areas associated with sub-pixels, are arranged; a light-emitting element layer disposed on one surface of the support substrate; and an encapsulation layer disposed on the light-emitting element layer. The encapsulation layer comprises a first inorganic layer covering the light-emitting element layer; an organic layer disposed on the first inorganic layer and overlapping the light-emitting element layer; and a second inorganic layer disposed on the first inorganic layer and covering the organic layer. A thickness of the first inorganic layer is smaller than a thickness of the second inorganic layer.

Abstract: A user access control method for an information system is proposed. The method may include processing login of a user using the information system, and acquiring a reference image obtained by capturing the logged-in user on the basis of a login time. The method may also include extracting reference feature information from the reference image and storing the reference feature information, and acquiring target images obtained by capturing a user using the information system at predetermined intervals. The method may further include extracting each target feature information from each target image; comparing each target feature information with the reference feature information to confirm whether or not each user using the information system at predetermined intervals is the same as the logged-in user, and controlling an access for the each user using the information system when the each user using the information system is not the same as the logged-in user.

Abstract: A display device includes a first substrate and a second substrate facing each other; and a filling layer disposed between the first substrate and the second substrate. The first substrate comprises a support substrate comprising a display area in which emission areas associated with sub-pixels, are arranged; a light-emitting element layer disposed on one surface of the support substrate; and an encapsulation layer disposed on the light-emitting element layer. The encapsulation layer comprises a first inorganic layer covering the light-emitting element layer; an organic layer disposed on the first inorganic layer and overlapping the light-emitting element layer; and a second inorganic layer disposed on the first inorganic layer and covering the organic layer. A thickness of the first inorganic layer is smaller than a thickness of the second inorganic layer.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: Provided is an irinotecan-loaded dual-reverse thermosensitive formulation, which is a dual-reverse thermosensitive hydrogel composition including nanoparticles including irinotecan and lipids; a hydrogel; and a stabilizer.

Abstract: Provided is an irinotecan-loaded dual-reverse thermosensitive formulation, which is a dual-reverse thermosensitive hydrogel composition including nanoparticles including irinotecan and lipids; a hydrogel; and a stabilizer.

Abstract: The present invention provides compositions and methods for the delivery of therapeutics to a cell or subject.

Abstract: Disclosed herein is a heating cabinet, in which a water collection tray is located in the heating cabinet such that the tray is not exposed to the outside, and water produced when an object is heated is collected in the water collection tray. The heating cabinet includes a main body defining a heating space in which an object to be heated is seated, a water collection tray provided under the heating space to be accommodated in the main body, and collecting water produced when the object is heated, and a front door rotatably coupled to a side of the main body to selectively close the open heating space while receiving the water collection tray, the front door having a guide part that is formed on a surface facing the heating space to guide the water, produced when the object is heated, to the water collection tray.

Abstract: A liquid crystal display that includes: a first substrate and a second substrate each including a display area and a non-display area, the display and non-display areas positioned opposite to each other; a plurality of data driver ICs formed in the non-display area of the first substrate; a plurality of data voltage supply lines connected to the data driver ICs and extending to the display area of the first substrate; a sealant positioned between the first substrate and the second substrate to surround the display areas; and a step compensating member formed outside the sealant on the non-display area of one of the first substrate and the second substrate, in which at least some of the data voltage supply lines extend under the sealant, and the step compensating member is positioned generally inline with the at least some of the data voltage supply lines.

Abstract: The present invention provides compositions and methods for the delivery of therapeutics to a cell or subject.