Patents by Inventor Jong Oh Kim
Jong Oh Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240130199Abstract: A display device includes a first substrate and a second substrate facing each other; and a filling layer disposed between the first substrate and the second substrate. The first substrate comprises a support substrate comprising a display area in which emission areas associated with sub-pixels, are arranged; a light-emitting element layer disposed on one surface of the support substrate; and an encapsulation layer disposed on the light-emitting element layer. The encapsulation layer comprises a first inorganic layer covering the light-emitting element layer; an organic layer disposed on the first inorganic layer and overlapping the light-emitting element layer; and a second inorganic layer disposed on the first inorganic layer and covering the organic layer. A thickness of the first inorganic layer is smaller than a thickness of the second inorganic layer.Type: ApplicationFiled: June 19, 2023Publication date: April 18, 2024Inventors: Gyu Min KIM, Jong Oh KIM, Jong Hyun PARK, Min Soo SEOL, Hee Dong CHOI, Tae Young HAM
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Publication number: 20240101369Abstract: An apparatus for supplying food ingredients according to the present disclosure includes a food ingredient lifting part configured to separate and move upward a food ingredient stack from a food ingredient cassette on which food ingredients including a plurality of stacked food ingredients are seated, a food ingredient separation part configured to suck and move upward a single sheet of a food ingredient from the food ingredient stack moved upward by the food ingredient lifting part, and a horizontal movement part configured to transfer forward the single sheet of the food ingredient moved upward by the food ingredient separation part.Type: ApplicationFiled: December 28, 2021Publication date: March 28, 2024Applicant: CJ CHEILJEDANG CORPORATIONInventors: Duk Jin CHANG, Min Soo LIM, Seung Yong KIM, Yong Ho JEON, Sang Oh KIM, Myoung Il KWAK, Jong Hwa LEE
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Publication number: 20240099354Abstract: A system for manufacturing edible food products according to the present disclosure includes a first food ingredient supply apparatus configured to separate a single sheet of a first food ingredient from a first food ingredient stack including a plurality of stacked first food ingredients and supply the single sheet of first food ingredient, a second food ingredient supply apparatus configured to separate a single sheet of a second food ingredient from a second food ingredient stack including a plurality of stacked second food ingredients and supply the single sheet of second food ingredient, and a pressing device configured to form an edible food product by pressing a semi-finished product formed by seating the supplied single sheet of the first food ingredient on the supplied single sheet of the second food ingredient.Type: ApplicationFiled: December 28, 2021Publication date: March 28, 2024Applicant: CJ CHEILJEDANG CORPORATIONInventors: Duk Jin CHANG, Min Soo LIM, Seung Yong KIM, Yong Ho JEON, Sang Oh KIM, Myoung Il KWAK, Jong Hwa LEE
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Publication number: 20240096474Abstract: A system for determining a tumor treatment plan using dose based on impulse is provided. The system comprises an information receiving unit classifying organs and a tumor of a medical image, and receiving three-dimensional image information including the organs and the tumor, and to receive physical property information including electrical conductivity and permittivity of the medical image; a dose receiving unit receiving a prescription dose information based on the impulse to the tumor; a candidate treatment plan establishing unit making at least one candidate treatment plan including number of treatment electrodes, position of the treatment electrode, treatment frequency, treatment voltage or current density and treatment time using the information received from the information receiving unit and the dose receiving unit; and a treatment plan determining unit determining a candidate treatment plan as a selected treatment plan from at least one candidate treatment plans.Type: ApplicationFiled: September 5, 2023Publication date: March 21, 2024Applicant: Fieldcure Co., Ltd.Inventors: Jong Hyun KIM, Geon OH
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Publication number: 20240083059Abstract: A cutting apparatus according to the present disclosure includes a cutting roller including a cutting body having a cylindrical shape and configured to rotate about an axis defined in a leftward/rightward direction, and cutting blades protruding outward in a radial direction of the cutting body further than a surface of the cutting body to cut an edible food product provided in a forward/rearward direction, and a cutting base part disposed at a position facing the cutting roller based on the edible food product to support the edible food product to be cut by the cutting roller.Type: ApplicationFiled: December 28, 2021Publication date: March 14, 2024Applicants: CJ CHEILJEDANG CORPORATION, CJ SEAFOOD CORPORATION, GREEN TECHNOLOGY CO., LTD.Inventors: Duk Jin CHANG, Min Soo LIM, Seung Yong KIM, Yong Ho JEON, Sang Oh KIM, Myoung Il KWAK, Jong Hwa LEE
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Publication number: 20240079413Abstract: A complementary thin film transistor (TFT) includes a substrate and a first TFT and a second TFT disposed on the substrate, wherein a first conductive semiconductor layer of the first TFT and a second gate electrode layer of the second TFT are disposed in the same layer and include the same material.Type: ApplicationFiled: August 31, 2023Publication date: March 7, 2024Inventors: Himchan OH, Jong-Heon YANG, Ji Hun CHOI, Seung Youl KANG, Yong Hae KIM, Jeho NA, Jaehyun MOON, Chan Woo PARK, Sung Haeng CHO, Jae-Eun PI, Chi-Sun HWANG
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Patent number: 11640992Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: GrantFiled: January 11, 2022Date of Patent: May 2, 2023Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.Inventors: Hamza Yilmaz, Jong Oh Kim
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Patent number: 11640994Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: GrantFiled: January 11, 2022Date of Patent: May 2, 2023Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.Inventors: Hamza Yilmaz, Jong Oh Kim
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Patent number: 11640993Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: GrantFiled: January 11, 2022Date of Patent: May 2, 2023Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.Inventors: Hamza Yilmaz, Jong Oh Kim
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Patent number: 11469313Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.Type: GrantFiled: January 19, 2021Date of Patent: October 11, 2022Assignee: IPOWER SEMICONDUCTORInventors: Hamza Yilmaz, Jong Oh Kim
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Publication number: 20220131000Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: ApplicationFiled: January 11, 2022Publication date: April 28, 2022Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.Inventors: HAMZA YILMAZ, JONG OH KIM
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Publication number: 20220130999Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: ApplicationFiled: January 11, 2022Publication date: April 28, 2022Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.Inventors: HAMZA YILMAZ, JONG OH KIM
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Publication number: 20220131001Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: ApplicationFiled: January 11, 2022Publication date: April 28, 2022Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.Inventors: HAMZA YILMAZ, JONG OH KIM
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Patent number: 11251297Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: GrantFiled: October 8, 2019Date of Patent: February 15, 2022Assignees: Ipower Semiconductor, Taiwan Semiconductor Co., Ltd.Inventors: Hamza Yilmaz, Jong Oh Kim
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Patent number: 11169474Abstract: A printer includes a printing unit to form a toner image on a printing medium, a fuser to apply heat and pressure to the printing medium that has passed through the printing unit to fuse the toner image on the printing medium, and a liquid-vapor chamber having a length in a width direction of the printing medium greater than a width of the printing medium. The liquid-vapor chamber has a heat absorber side to face the printing medium to absorb heat from the printing medium, a condenser side apart from the heat absorber side in an opposite direction not facing the printing medium to form an inner space between the condenser side and the heat absorber side, and a working fluid sealed in the inner space and to undergo a liquid-vapor phase change by moving between the heat absorber side and the condenser side, to absorb heat from the printing medium to cool the printing medium that has passed through the fuser.Type: GrantFiled: November 27, 2018Date of Patent: November 9, 2021Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventor: Jong-Oh Kim
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Publication number: 20210226041Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.Type: ApplicationFiled: January 19, 2021Publication date: July 22, 2021Applicant: IPOWER SEMICONDUCTORInventors: HAMZA YILMAZ, JONG OH KIM
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Publication number: 20210109465Abstract: A printer includes a printing unit to form a toner image on a printing medium, a fuser to apply heat and pressure to the printing medium that has passed through the printing unit to fuse the toner image on the printing medium, and a liquid-vapor chamber having a length in a width direction of the printing medium greater than a width of the printing medium. The liquid-vapor chamber has a heat absorber side to face the printing medium to absorb heat from the printing medium, a condenser side apart from the heat absorber side in an opposite direction not facing the printing medium to form an inner space between the condenser side and the heat absorber side, and a working fluid sealed in the inner space and to undergo a liquid-vapor phase change by moving between the heat absorber side and the condenser side, to absorb heat from the printing medium to cool the printing medium that has passed through the fuser.Type: ApplicationFiled: November 27, 2018Publication date: April 15, 2021Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventor: Jong-Oh KIM
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Publication number: 20200044078Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.Type: ApplicationFiled: October 8, 2019Publication date: February 6, 2020Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.Inventors: HAMZA YILMAZ, JONG OH KIM
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Patent number: 10172943Abstract: Provided is an irinotecan-loaded dual-reverse thermosensitive formulation, which is a dual-reverse thermosensitive hydrogel composition including nanoparticles including irinotecan and lipids; a hydrogel; and a stabilizer.Type: GrantFiled: January 21, 2016Date of Patent: January 8, 2019Assignee: INDUSTRY—UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUSInventors: Han-Gon Choi, Fakhar Ud Din, Dong Wuk Kim, Dong Shik Kim, Chul Soon Yong, Jong Oh Kim, Yu-Kyoung Oh
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Publication number: 20180147282Abstract: Provided is an irinotecan-loaded dual-reverse thermosensitive formulation, which is a dual-reverse thermosensitive hydrogel composition including nanoparticles including irinotecan and lipids; a hydrogel; and a stabilizer.Type: ApplicationFiled: January 21, 2016Publication date: May 31, 2018Inventors: Han-Gon CHOI, Fakhar UD DIN, Dong Wuk KIM, Dong Shik KIM, Chul Soon YONG, Jong Oh KIM, Yu-Kyoung OH