Patents by Inventor Jong Oh Kim

Jong Oh Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12157121
    Abstract: The present invention relates to the structure of an analysis plate applied to a high-speed polymerase chain reaction (PCR), and to a PCR analysis plate used for implementing an analysis of a real-time PCR, a real-time nested PCR and a post-PCR lateral flow hybridization reaction. The present invention is provided with: a check valve for enabling the maintaining of positive pressure when an elastic film expands into a convex form by having a solution pushed therein by the positive pressure; a lateral flow analysis module for analyzing a post-PCR follow-up PCR or lateral flow; and a shut-off valve enabling the controlling of the movement of the solution after each reaction ends.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: December 3, 2024
    Assignee: Bioneer Corporation
    Inventors: Han Oh Park, Jong Kab Kim, Yang Won Lee, Sang Ryoung Park
  • Patent number: 12133891
    Abstract: Disclosed herein are a microbubble-extracellular vesicle complex, a production method therefor, and a system for driving the same. In one aspect, preferred microbubble-extracellular vesicle complexes may comprise an ultrasound contrast agent-based microbubble, an extracellular cell derived from a natural killer cell (NK cell), a human glial cell, or a human mesenchymal stem cell, and a coupling medium and can be derive in a 3D mode using ultrasonic waves and deliver a drug loaded in the extracellular vesicle to a target site.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: November 5, 2024
    Assignees: INDUSTRY FOUNDATION OF CHONNAM NATIONAL UNIVERSITY, KOREA INSTITUTE OF MEDICAL MICROROBOTICS, Johns Hopkins University
    Inventors: Eun Pyo Choi, Jong Oh Park, Chang Sei Kim, You Hee Choi, Byung Jeon Kang, Ho Yong Kim, Hyeong Woo Song, Dae Won Jung, Han Sol Lee, Deok Ho Kim, Min Jae Do
  • Patent number: 12128585
    Abstract: The present invention relates to a manufacturing device for manufacturing a large amount of micro-scaffolds for a long period of time such that stable and uniform particles can be fabricated. The manufacturing device comprises: a first solution storage portion for storing a polymer support structure solution; a second solution storage portion for storing an emulsifier solution; a gas storage portion connected to each of the first solution storage portion and the second solution storage portion; a pressure control portion for controlling the pressure of the transporting gas flowing into the first solution storage portion and the second solution storage portion from the pressurization portion, respectively; a scaffold injector portion for receiving the polymer support structure solution and the emulsifier solution provided by the transporting gas, respectively; and a scaffold generating portion for receiving the scaffold dispersion discharged through the scaffold injection portion.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: October 29, 2024
    Assignees: INDUSTRY FOUNDATION OF CHONNAM NATIONAL UNIVERSITY, BIOT KOREA INC.
    Inventors: Eun Pyo Choi, Jong Oh Park, Chang Sei Kim, Byung Jeon Kang, Seok Jae Kim, Gwang Jun Go, Yeong Jun Chang
  • Patent number: 12102119
    Abstract: An aerosol-generating article according to an embodiment may include a medium portion, a front end plug disposed to face an upstream end of the medium portion, and a filter portion disposed to face a downstream end of the medium portion, wherein the front end plug includes a channel extending from the upstream end to the downstream end.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: October 1, 2024
    Assignee: KT&G CORPORATION
    Inventors: Jin Chul Yang, Soo Ho Kim, Jong Yeol Kim, Man Seok Seo, Ki Jin Ahn, In Hyeog Oh
  • Patent number: 12100689
    Abstract: An apparatus for manufacturing a light emitting display device includes a substrate transfer stage including a plurality of support plates arranged at an interval in a first direction, each of the plurality of support plates extending in a second direction; and at least one electric-field application module disposed on at least one side of the substrate transfer stage. The at least one electric-field application module includes a probe head including at least one probe pin; and a driver connected to the probe head to move the probe head at least up and down.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 24, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jong Hyuk Kang, Hae Yun Choi, Han Su Kim, Eun A Yang, Hyun Min Cho, Keun Kyu Song, Jin Oh Kwag
  • Patent number: 12080693
    Abstract: A display device and a method of manufacturing the same are provided. The display device comprises a first area which extends in a first direction, a second area which extends in the first direction and is alongside the first area in a second direction intersecting the first direction, at least one first light emitting element in the first area, at least one second light emitting element in the second area, at least one first wiring coupled to an end of the first light emitting element in the first area and that extends in the first direction and at least one second wiring coupled to an end of the second light emitting element in the second area and that extends in the first direction, wherein the first wiring and the second wiring are electrically isolated from each other.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 3, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won Ho Lee, Yo Han Lee, Jong Hyuk Kang, Jin Oh Kwag, Hyun Deok Im, Hyun Min Cho, Won Kyu Kim, Keun Kyu Song
  • Publication number: 20240289455
    Abstract: Disclosed herein is a method for detecting an anomaly state based on screen output. The method includes receiving the output screen of a target device to be monitored, setting a target region to be examined in the output screen of the target device to be monitored, calculating a feature value vector corresponding to the state of the target region to be examined, calculating an anomaly score using a pretrained auto-encoder by receiving the feature value vector as input, and determining whether the target device to be monitored is anomalous using the anomaly score.
    Type: Application
    Filed: June 14, 2023
    Publication date: August 29, 2024
    Inventors: Hyung-Kwan KIM, Jong-Won CHOI, Seung-Oh CHOI, Jeong-Han YUN, Won-Seok HWANG, Woo-Myo LEE, Byung-Gil MIN, Hyeok-Ki SHIN
  • Patent number: 12070290
    Abstract: The present invention relates to a medical robot system capable of effectively removing a calcified thrombus in a blood vessel. The present invention proposes a new guide-wired helical microrobot for mechanical thrombectomy applied to a calcified thrombus. Also, the present invention proposes an electromagnetic navigation system (ENS) which uses a high frequency operation that is based on a resonant effect in order to enhance the boring force of a microrobot. The microrobot system of the present invention can precisely tunnel through a blood vessel blockage site by means of the electromagnetic navigation system without damaging blood vessel walls. The microrobot system of the present invention has a wide range of applications including not only for thrombosis, but also thromboangiitis obliterans caused by vasoocclusion, cerebral infarction, strokes, angina or myocardial infarction, peripheral artery occlusive disease, or atherosclerosis, etc.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: August 27, 2024
    Assignee: INDUSTRY FOUNDATION OF CHONNAM NATIONAL UNIVERSITY
    Inventors: Chang Sei Kim, Jong Oh Park, Eun Pyo Choi, Byung Jeon Kang, Kim Tien Nguyen, Gwang Jun Go
  • Publication number: 20240152585
    Abstract: A user access control method for an information system is proposed. The method may include processing login of a user using the information system, and acquiring a reference image obtained by capturing the logged-in user on the basis of a login time. The method may also include extracting reference feature information from the reference image and storing the reference feature information, and acquiring target images obtained by capturing a user using the information system at predetermined intervals. The method may further include extracting each target feature information from each target image; comparing each target feature information with the reference feature information to confirm whether or not each user using the information system at predetermined intervals is the same as the logged-in user, and controlling an access for the each user using the information system when the each user using the information system is not the same as the logged-in user.
    Type: Application
    Filed: October 24, 2023
    Publication date: May 9, 2024
    Inventors: Gyu Dong PARK, Ho Cheol JEON, Jong Oh KIM, Hyoek Jin CHOI
  • Publication number: 20240130199
    Abstract: A display device includes a first substrate and a second substrate facing each other; and a filling layer disposed between the first substrate and the second substrate. The first substrate comprises a support substrate comprising a display area in which emission areas associated with sub-pixels, are arranged; a light-emitting element layer disposed on one surface of the support substrate; and an encapsulation layer disposed on the light-emitting element layer. The encapsulation layer comprises a first inorganic layer covering the light-emitting element layer; an organic layer disposed on the first inorganic layer and overlapping the light-emitting element layer; and a second inorganic layer disposed on the first inorganic layer and covering the organic layer. A thickness of the first inorganic layer is smaller than a thickness of the second inorganic layer.
    Type: Application
    Filed: June 19, 2023
    Publication date: April 18, 2024
    Inventors: Gyu Min KIM, Jong Oh KIM, Jong Hyun PARK, Min Soo SEOL, Hee Dong CHOI, Tae Young HAM
  • Patent number: 11640993
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: May 2, 2023
    Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Hamza Yilmaz, Jong Oh Kim
  • Patent number: 11640994
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: May 2, 2023
    Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Hamza Yilmaz, Jong Oh Kim
  • Patent number: 11640992
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: May 2, 2023
    Assignees: IPOWER SEMICONDUCTOR, TAIWAN SEMICONDUCTOR CO., LTD.
    Inventors: Hamza Yilmaz, Jong Oh Kim
  • Patent number: 11469313
    Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: October 11, 2022
    Assignee: IPOWER SEMICONDUCTOR
    Inventors: Hamza Yilmaz, Jong Oh Kim
  • Publication number: 20220131001
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 28, 2022
    Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.
    Inventors: HAMZA YILMAZ, JONG OH KIM
  • Publication number: 20220130999
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 28, 2022
    Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.
    Inventors: HAMZA YILMAZ, JONG OH KIM
  • Publication number: 20220131000
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Application
    Filed: January 11, 2022
    Publication date: April 28, 2022
    Applicants: IPOWER SEMICONDUCTOR, Taiwan Semiconductor Co., Ltd.
    Inventors: HAMZA YILMAZ, JONG OH KIM
  • Patent number: 11251297
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: February 15, 2022
    Assignees: Ipower Semiconductor, Taiwan Semiconductor Co., Ltd.
    Inventors: Hamza Yilmaz, Jong Oh Kim
  • Patent number: 11169474
    Abstract: A printer includes a printing unit to form a toner image on a printing medium, a fuser to apply heat and pressure to the printing medium that has passed through the printing unit to fuse the toner image on the printing medium, and a liquid-vapor chamber having a length in a width direction of the printing medium greater than a width of the printing medium. The liquid-vapor chamber has a heat absorber side to face the printing medium to absorb heat from the printing medium, a condenser side apart from the heat absorber side in an opposite direction not facing the printing medium to form an inner space between the condenser side and the heat absorber side, and a working fluid sealed in the inner space and to undergo a liquid-vapor phase change by moving between the heat absorber side and the condenser side, to absorb heat from the printing medium to cool the printing medium that has passed through the fuser.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 9, 2021
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventor: Jong-Oh Kim
  • Publication number: 20210226041
    Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.
    Type: Application
    Filed: January 19, 2021
    Publication date: July 22, 2021
    Applicant: IPOWER SEMICONDUCTOR
    Inventors: HAMZA YILMAZ, JONG OH KIM