Abstract: A thin film transistor includes a first gate electrode on a substrate, a gate insulating film on the first gate electrode, a first active layer on the gate insulating film, a drain electrode on one side of the first active layer, a sidewall spacer on a side wall of the drain electrode, and a first source electrode provided on the other side of the first active layer and a sidewall of the sidewall spacer.

Abstract: In one aspect, an electric furnace is provided with a double type melting furnace, which includes: a first upper cell that forms a first upper space of a first melting furnace in which a first iron source is introduced and molten; a second upper cell that is disposed in a horizontal direction of the first upper cell and forms a second upper space of a second melting furnace in which a second iron source is introduced and molten; a lower cell that is combined with lower portions of the first upper cell and the second upper cell and forms a single integrated space in which a first lower space of the first melting furnace and a second lower space of the second melting furnace are integrated; and a partition wall unit that is installed to vertically move up and down between the first upper cell and the second upper cell, and separates the first lower space of the first melting furnace and the second lower space of the second melting furnace, although both of the lower spaces are integrally formed by the lower cel

Abstract: According to an embodiment of the present disclosure, a method of detecting a white matter lesion based on a medical image performed by a computing device is disclosed. The method may include: receiving a medical image including at least one brain region; and estimating a first white matter lesion and a second white matter lesion based on the medical image using a pre-trained neural network model.

Abstract: The present invention relates to a system structure capable of performing real-time detection of nucleic acid extraction and amplification reactions and amplified results in a device for implementing a polymerase chain reaction (PCR).

Abstract: The present invention relates to the structure of an analysis plate applied to a high-speed polymerase chain reaction (PCR), and to a PCR analysis plate used for implementing an analysis of a real-time PCR, a real-time nested PCR and a post-PCR lateral flow hybridization reaction. The present invention is provided with: a check valve for enabling the maintaining of positive pressure when an elastic film expands into a convex form by having a solution pushed therein by the positive pressure; a lateral flow analysis module for analyzing a post-PCR follow-up PCR or lateral flow; and a shut-off valve enabling the controlling of the movement of the solution after each reaction ends.

Abstract: A display device includes a substrate, a semiconductor layer, an insulating layer, and a conductive layer. The semiconductor layer is disposed on the substrate, includes a channel of a first transistor, and includes a channel of a second transistor. The insulating layer is disposed on the semiconductor layer. The conductive layer is disposed on the insulating layer, includes a gate electrode of the first transistor, and includes a gate electrode of the second transistor. The channel of the first transistor includes a first first-element impurity ion and a second-element impurity ion different from the first first-element impurity ion. The channel of the second transistor includes a second first-element impurity ion identical to the first first-element impurity ion.

Abstract: Provided is a method of preparing a silicon composite. The method of preparing a silicon composite includes forming a silicon solution by wet-grinding a silicon raw material; forming silicon fine powder by spray-drying the silicon solution; disintegrating the silicon fine powder; forming a dispersion by coating the silicon fine powder with a first pitch; forming a first composite by coating the dispersion with a second pitch; forming a second composite by carbonizing the first composite; and classifying the second composite according to a preset particle size reference.

Abstract: A user access control method for an information system is proposed. The method may include processing login of a user using the information system, and acquiring a reference image obtained by capturing the logged-in user on the basis of a login time. The method may also include extracting reference feature information from the reference image and storing the reference feature information, and acquiring target images obtained by capturing a user using the information system at predetermined intervals. The method may further include extracting each target feature information from each target image; comparing each target feature information with the reference feature information to confirm whether or not each user using the information system at predetermined intervals is the same as the logged-in user, and controlling an access for the each user using the information system when the each user using the information system is not the same as the logged-in user.

Abstract: A display device includes a first substrate and a second substrate facing each other; and a filling layer disposed between the first substrate and the second substrate. The first substrate comprises a support substrate comprising a display area in which emission areas associated with sub-pixels, are arranged; a light-emitting element layer disposed on one surface of the support substrate; and an encapsulation layer disposed on the light-emitting element layer. The encapsulation layer comprises a first inorganic layer covering the light-emitting element layer; an organic layer disposed on the first inorganic layer and overlapping the light-emitting element layer; and a second inorganic layer disposed on the first inorganic layer and covering the organic layer. A thickness of the first inorganic layer is smaller than a thickness of the second inorganic layer.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

Abstract: A printer includes a printing unit to form a toner image on a printing medium, a fuser to apply heat and pressure to the printing medium that has passed through the printing unit to fuse the toner image on the printing medium, and a liquid-vapor chamber having a length in a width direction of the printing medium greater than a width of the printing medium. The liquid-vapor chamber has a heat absorber side to face the printing medium to absorb heat from the printing medium, a condenser side apart from the heat absorber side in an opposite direction not facing the printing medium to form an inner space between the condenser side and the heat absorber side, and a working fluid sealed in the inner space and to undergo a liquid-vapor phase change by moving between the heat absorber side and the condenser side, to absorb heat from the printing medium to cool the printing medium that has passed through the fuser.

Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.

Abstract: A printer includes a printing unit to form a toner image on a printing medium, a fuser to apply heat and pressure to the printing medium that has passed through the printing unit to fuse the toner image on the printing medium, and a liquid-vapor chamber having a length in a width direction of the printing medium greater than a width of the printing medium. The liquid-vapor chamber has a heat absorber side to face the printing medium to absorb heat from the printing medium, a condenser side apart from the heat absorber side in an opposite direction not facing the printing medium to form an inner space between the condenser side and the heat absorber side, and a working fluid sealed in the inner space and to undergo a liquid-vapor phase change by moving between the heat absorber side and the condenser side, to absorb heat from the printing medium to cool the printing medium that has passed through the fuser.